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1. 发明授权

US08711982B1 Amplitude-shift-keying (ASK) envelope detector and demodulation circuits 有权
标题翻译：幅移键控（ASK）包络检波器和解调电路
公开(公告)号：US08711982B1
公开(公告)日：2014-04-29
申请号：US13790951
申请日：2013-03-08
申请人： Hong Kong Applied Science & Technology Research Institute Company Limited
发明人： Guangjie Cai , Leung Ling (Alan) Pun , Tat Fu Chan
IPC分类号： H03D1/24 , H03D1/00
CPC分类号： H03D1/18
摘要： An envelope detector receives an input that is an Amplitude-Modulated (AM) or Amplitude-Shift-Keying (ASK) coded signal. Each channel has a sample switch and a diode that charge an internal sampling capacitor. A hold switch connects the internal sampling capacitor to a summing output capacitor or to a post-processing circuit. A reset switch discharges the internal sampling capacitor after each sample. Two or more channels may be time multiplexed to sample alternate cycles of the input, and then their outputs combined by the summing output capacitor or by the post-processing circuit. The diodes may be reversed to detect the negative envelope rather than the positive envelope. Clocks for the switches may be generated from the input, or may be from a separate clock source. Since the sampling window is open for a whole input cycle, the clock source is insensitive to phase error.
摘要翻译：包络检测器接收作为幅度调制（AM）或幅移键控（ASK）编码信号的输入。每个通道都有一个采样开关和一个对内部采样电容充电的二极管。保持开关将内部采样电容器连接到求和输出电容器或后处理电路。每个样品后，复位开关对内部采样电容放电。两个或多个通道可以被时间复用以对输入的交替周期进行采样，然后它们的输出由加法输出电容器或后处理电路组合。二极管可以反向以检测负信封而不是正信封。用于开关的时钟可以从输入产生，或者可以来自单独的时钟源。由于采样窗口为整个输入周期打开，因此时钟源对相位误差不敏感。

2. 发明授权

US08643432B1 Op-Amp sharing by swapping trans-conductance cells 有权
标题翻译：通过交换反电导单元进行Op-Amp共享
公开(公告)号：US08643432B1
公开(公告)日：2014-02-04
申请号：US13560455
申请日：2012-07-27
申请人： Chi Hong Chan , Chi Fat Chan , Gordon Chung
发明人： Chi Hong Chan , Chi Fat Chan , Gordon Chung
IPC分类号： H03F1/02 , H03F3/45
CPC分类号： H03F3/005 , H03F3/45179 , H03F3/45192 , H03F3/45636 , H03F2203/45544 , H03F2203/45551 , H03F2203/45616 , H03F2203/45631 , H03F2203/45644 , H03F2203/45702 , H03F2203/45724 , H03F2203/45726 , H03F2203/45728
摘要： A two-stage op amp has a transconductance cell in a second stage modified to match a transconductance cell in a first stage. A transconductance swap network is inserted between transconductance cells and trans-impedance cells, such as current-steering networks, current mirrors, or drivers connected to the transconductance cells. The transconductance swap network directly connects the first transconductance cell to the first stage trans-impedance cell during a second clock phase, but crosses-over the first transconductance cell to the second-stage trans-impedance cell during a first clock phase. A first switched-capacitor network drives the gates of differential transistors in the first transconductance cell by alternately sampling an input and feedback, and equalizing to reset inputs. A second first switched-capacitor network drives differential transistors in the second transconductance cell, but during opposite clock phases. Two independent inputs are sampled by the switched-capacitor networks and alternately amplified by swapping connections within the shared op amp.
摘要翻译：两级运算放大器具有在第一级修改为匹配跨导单元的第二级中的跨导单元。在跨导单元和跨阻抗单元之间插入跨导互换网络，例如电流转向网络，电流镜或连接到跨导单元的驱动器。跨导互换网络在第二时钟相位期间将第一跨导单元直接连接到第一级跨阻抗单元，但是在第一时钟阶段期间，跨越第一跨导单元跨越第二级跨阻抗单元。第一开关电容器网络通过交替地对输入和反馈进行采样并均衡复位输入来驱动第一跨导单元中的差分晶体管的栅极。第二个第一个开关电容网络驱动第二跨导单元中的差分晶体管，但是在相反的时钟阶段。两个独立的输入由开关电容网络采样，并通过交换共享运算放大器内的连接来交替放大。

3. 发明授权

US08421658B1 Parallel pipelined calculation of two calibration values during the prior conversion cycle in a successive-approximation-register analog-to-digital converter (SAR-ADC) 有权
标题翻译：在逐次逼近寄存器模数转换器（SAR-ADC）中，在先前的转换周期内对两个校准值进行并行流水线计算，
公开(公告)号：US08421658B1
公开(公告)日：2013-04-16
申请号：US13304346
申请日：2011-11-24
申请人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
发明人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/1047 , H03M1/468
摘要： A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.
摘要翻译：逐次近似寄存器模数转换器（SAR-ADC）预测在未来周期中使用的补偿值。补偿值用于校准Y侧电容器阵列中的电容器，以补偿二进制加权的X侧电容器阵列中的电容误差。两个计算引擎预先计算下一个要转换的位的预测0和预测-1补偿值。在比较器确定当前位的当前周期结束时，比较器还控制多路复用器来选择两个预测补偿值之一。因此，补偿值在下一位循环开始时可用，消除了长时间的计算延迟。在校准期间计算要转换的第一位的补偿值，例如MSB。其他位的补偿值依赖于数据。在校准期间累积校准值，以生成要转换的第一个位的第一个转换补偿值。

4. 发明授权

US09054521B2 Electro-static-discharge (ESD) protection structure with stacked implant junction transistor and parallel resistor and diode paths to lower trigger voltage and raise holding volatge 有权
标题翻译：具有堆叠式注入结晶体管和并联电阻器和二极管路径的静电放电（ESD）保护结构，以降低触发电压并提高保持电压
公开(公告)号：US09054521B2
公开(公告)日：2015-06-09
申请号：US13925956
申请日：2013-06-25
申请人： Hong Kong Applied Science & Technology Research Institute Company Limited
发明人： Xiao Huo , Beiping Yan , Xiaowu Cai
IPC分类号： H02H9/00 , H02H9/04 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0248 , H01L27/0259
摘要： An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode.
摘要翻译：静电放电（ESD）保护电路具有垂直NPN晶体管，其具有由N +源极区域下的深p型注入产生的浮动p型基极。深p型植入物可以是标准CMOS工艺中的ESD注入。 p型注入提供了低的初始瞬态触发电压，但是保持电压可能太低，造成闩锁问题。通过将垂直NPN晶体管的发射极连接到并联电阻和二极管路径，保持电压提高约一伏。当垂直NPN晶体管被触发时，其电流最初流过电阻器，当电流上升时，通过电阻产生增加的电压降。一旦电阻上的电压达到0.5伏特，与电阻并联的二极管就会正向偏置，并分流比电阻更高的电流，提高保持电压。钳位晶体管可以替代二极管。

5. 发明授权

US08483390B2 Systems and methods for broadcast encryption optimization and scalability 有权
标题翻译：用于广播加密优化和可扩展性的系统和方法
公开(公告)号：US08483390B2
公开(公告)日：2013-07-09
申请号：US13249237
申请日：2011-09-30
申请人： Victor Keh Wei Wei , Zhibin Lei , Yiu Wing Wat , Wing Pan Leung
发明人： Victor Keh Wei Wei , Zhibin Lei , Yiu Wing Wat , Wing Pan Leung
IPC分类号： H04L9/00
CPC分类号： H04L9/0833 , H04L9/3066 , H04L2209/601
摘要： A content distribution method with broadcast encryption, comprising: executing a setup process, comprising: generating public domain parameters, generating a server secret, and generating one or more client private keys, one for each content receiving client; executing an encryption process, comprising: generating a cipher text using the server secret, a subscriber set, and a randomness, the cipher text being constant and independent of total number of content receiving clients in a distribution network, generating a plain text using the server secret and the randomness, encrypting an original content into an encrypted content using the plain text; distributing the client private keys to the content receiving clients; distributing the cipher text to the content receiving clients; broadcasting the encrypted content through the distribution network; and executing a decryption process on the encrypted content by each of the content receiving clients in the distribution network.
摘要翻译：一种具有广播加密的内容分发方法，包括：执行建立过程，包括：生成公共域参数，生成服务器密码，以及生成一个或多个客户端私钥，每个内容接收客户端一个; 执行加密处理，包括：使用所述服务器秘密，订户集合和随机性生成密文，所述密文是恒定的，并且不依赖于分发网络中的接收客户端的总数，使用所述服务器生成纯文本秘密和随机性，使用纯文本将原始内容加密成加密内容; 将客户端私钥分发到内容接收客户端; 将密文分发到内容接收客户端; 通过分发网络广播加密的内容; 以及通过分发网络中的每个内容接收客户端对加密的内容执行解密处理。

6. 发明授权

US08421660B1 Configurable cascading sigma delta analog-to digital converter (ADC) for adjusting power and performance 有权
标题翻译：可配置的级联Σ-Δ模数转换器（ADC），用于调节功率和性能
公开(公告)号：US08421660B1
公开(公告)日：2013-04-16
申请号：US13304526
申请日：2011-11-25
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Andrea Baschirotto
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Andrea Baschirotto
IPC分类号： H03M3/00
CPC分类号： H03M3/392 , H03M3/414
摘要： A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.
摘要翻译：级联的Σ-Δ调制器具有多个调制器环路，其具有一组或两组积分器，加法器和定标器，以及产生回路输出的量化器。对每个环路输入多路复用器，从一个先前的循环中选择一个总体输入或一个环路输出，使调制器回路串联级联或单独运行。在每个调制器环路之后，滤波器配置的多路复用器选择该环路的输出或来自任何先前循环的回路输出或零。每个过滤器配置的多路复用器驱动输入到修改后的CIC过滤器。修改的CIC滤波器具有接收第一滤波器配置多路复用器输出的初始延迟级，以及每个接收连续的滤波器配置多路复用器输出的连续积分器级。改进的CIC滤波器是数字变换滤波器和级联积分器（CIC） - 滤波器（Cascaded-Integrator-Comb，CIC）滤波器的组合。调制解调器环路已经掉电，用于低性能配置或级联在一起以实现更高性能的配置。

7. 发明授权

US08416107B1 Charge compensation calibration for high resolution data converter 有权
标题翻译：高分辨率数据转换器的充电补偿校准
公开(公告)号：US08416107B1
公开(公告)日：2013-04-09
申请号：US13247119
申请日：2011-09-28
申请人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
发明人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译：校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容复制为终端电容，并且上下组之间的中间电容也被复制作为替代电容器。在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。温度计值反转到X阵列，但在Y阵列上保持不变。测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。

8. 发明授权

US09054485B1 Asymmetric edge compensation of both anode and cathode terminals of a vertical-cavity surface-emitting laser (VCSEL) diode 有权
标题翻译：垂直腔表面发射激光器（VCSEL）二极管的阳极和阴极端子的非对称边缘补偿
公开(公告)号：US09054485B1
公开(公告)日：2015-06-09
申请号：US14488444
申请日：2014-09-17
申请人： Hong Kong Applied Science & Technology Research Institute Company Limited
发明人： Kwan Ting Ng
IPC分类号： H01S3/13 , H01S5/042 , H01S5/183
CPC分类号： H01S5/042 , H01S5/0427 , H01S5/06213 , H01S5/06226 , H01S5/183
摘要： A laser driver circuit compensates for non-linear behavior of Vertical-Cavity Surface-Emitting Laser (VCSEL) devices. A VCSEL has an internal parasitic capacitance that is charged while the VCSEL is on. When the VCSEL turns off, this internal parasitic capacitor discharges, keeping the VCSEL on longer, increasing the physical turn-off or fall time. The laser driver circuit compensates for the slower fall time by modulating both anode and cathode terminals of the VCSEL as the VCSEL is turned on and off. Both plates of the internal parasitic capacitor are discharged at turn off, cutting the parasitic discharge time in half. A cathode driver transistor modulates the cathode voltage while a source-follower transistor modulates the anode voltage. A modulating current may be switched using a current mirror structure. Multiple source-follower transistors may be selectable in parallel, with switches to select the total anode current, allowing for programmable compensation of the fall time.
摘要翻译：激光驱动电路补偿垂直腔表面发射激光器（VCSEL）器件的非线性特性。 VCSEL有一个内部寄生电容，在VCSEL导通时，该寄生电容充电。当VCSEL关断时，内部寄生电容放电，保持VCSEL更长时间，增加物理关断或下降时间。激光驱动电路通过在VCSEL导通和关断时调制VCSEL的阳极和阴极端子来补偿较慢的下降时间。内部寄生电容器的两片放电关闭，将寄生放电时间减半。阴极驱动晶体管调制阴极电压，而源极 - 跟随器晶体管调制阳极电压。可以使用电流镜结构来切换调制电流。多个源极跟随器晶体管可以并联选择，开关选择总阳极电流，允许对下降时间的可编程补偿。

9. 发明授权

US08780590B2 Output current estimation for an isolated flyback converter with variable switching frequency control and duty cycle adjustment for both PWM and PFM modes 有权
标题翻译：用于PWM和PFM模式的具有可变开关频率控制和占空比调整的隔离反激式转换器的输出电流估计
公开(公告)号：US08780590B2
公开(公告)日：2014-07-15
申请号：US13462986
申请日：2012-05-03
申请人： Wai Kit (Victor) So , Hing Kit Kwan , Chik Wai (David) Ng , Po Wah (Patrick) Chang
发明人： Wai Kit (Victor) So , Hing Kit Kwan , Chik Wai (David) Ng , Po Wah (Patrick) Chang
IPC分类号： H02M3/335
CPC分类号： H02M3/33507 , H02M2001/0009
摘要： A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching.
摘要翻译：回扫功率转换器具有电流估算控制回路，其感测变压器中的主要输出电流以控制次级输出。初级侧控制电路通过变压器开启和关闭一次电流。通过变压器的辅助绕组的二次电流流过的放电时间是通过对用于拐点的辅助回路上的分压器进行采样而产生的。通过将放电时间乘以与开关频率成比例的电流并与具有开关频率的锯齿波信号进行比较来计算归一化占空比。初级侧电压的峰值从初级电流回路感测并转换为电流并乘以归一化的占空比以产生估计电流。误差放大器将估计电流与参考值进行比较，以调整振荡器频率和峰值电流以控制主开关。

10. 发明授权

US08471744B1 Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge 有权
标题翻译：减少残差偏移Σ-Δ模数转换器（ADC），在后沿积分相位结束时具有斩波定时
公开(公告)号：US08471744B1
公开(公告)日：2013-06-25
申请号：US13308737
申请日：2011-12-01
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan
IPC分类号： H03M3/00
CPC分类号： H03M3/34 , H03M3/43 , H03M3/454
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译：模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。

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