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    • 2. 发明申请
    • APPARATUS FOR ANALYSIS AND EVALUATION OF CHARACTERISTICS OF SERIES-CONNECTED SOLAR BATTERY CELLS
    • 串联太阳能电池的特性分析与评估装置
    • US20110257912A1
    • 2011-10-20
    • US13026009
    • 2011-02-11
    • Hideyo NAKAMURA
    • Hideyo NAKAMURA
    • G06F19/00
    • G06F17/5018H02S50/10
    • An apparatus for estimating and evaluating characteristics of large-area series-connected solar battery cells from a measured current-voltage characteristic of a small-area single cell, includes an analysis model construction unit, an analysis operation unit and an evaluation unit. The construction unit reads shape parameters and material physical properties of the cells and automatically constructs a finite element method model. The operation unit obtains a current at a voltage based on the measured characteristic, sets the current as a current load, calculates potential distributions of transparent electrode and rear electrode of the cells, corrects the current load based on a difference between the distributions and the measured characteristic, recalculates the distributions based on the corrected current load, and repeats the recalculation until the distributions converge. The evaluation unit evaluates whether a converged calculation result is a pattern exhibiting a desired current-voltage characteristic of the cells.
    • 一种用于从小区域单电池的测量电流 - 电压特性估计和评估大面积串联太阳能电池单元的特性的装置,包括分析模型构建单元,分析运算单元和评估单元。 施工单位读取细胞的形状参数和材料物理性质,并自动构建有限元方法模型。 操作单元基于测量特性获得电压,将电流设置为电流负载,计算电池的透明电极和后电极的电位分布,根据分布和测量值之间的差异校正电流负载 特征,基于校正的当前负载重新计算分布,并重复重新计算直到分布收敛。 评估单元评估会聚的计算结果是否是呈现电池的期望的电流 - 电压特性的图案。
    • 5. 发明申请
    • LOGIC CIRCUIT
    • 逻辑电路
    • US20110109345A1
    • 2011-05-12
    • US13004480
    • 2011-01-11
    • Haruo KAWAKAMI
    • Haruo KAWAKAMI
    • H03K19/003
    • H03K19/02H03K3/313
    • A logic circuit includes two two-terminal switching devices and receives first and second pulses as inputs. Each of the two devices has two different stable resistivity values for each applied voltage that is greater than a first threshold voltage (Vth1) and is smaller than a second threshold voltage (Vth2) that is larger than Vth1. Each switching device, when a voltage less than or equal to Vth1 is applied, becomes in a first state having the higher resistivity of the two resistivity values, whereas when a voltage more than or equal to Vth2 is applied, becomes in a second state having the lower resistivity of the two resistivity values. The two devices are connected in series in a direction with uniform polarity to each other. The first and second states are selectively generated in the first and second devices by a combination of inputs of the first and second pulses.
    • 逻辑电路包括两个两端开关器件,并接收第一和第二脉冲作为输入。 两个装置中的每一个对于大于第一阈值电压(Vth1)的每个施加的电压具有两个不同的稳定电阻率值,并且小于大于Vth1的第二阈值电压(Vth2)。 当施加小于或等于Vth1的电压时,每个开关装置变为具有两个电阻率值的较高电阻率的第一状态,而当施加大于或等于Vth2的电压时,变为具有 两个电阻率值的电阻率较低。 两个装置在彼此具有均匀极性的方向上串联连接。 第一和第二状态通过第一和第二脉冲的输入的组合在第一和第二装置中选择性地产生。
    • 7. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20100264455A1
    • 2010-10-21
    • US12824541
    • 2010-06-28
    • Haruo NAKAZAWAKazuo SHIMOYAMAManabu TAKEI
    • Haruo NAKAZAWAKazuo SHIMOYAMAManabu TAKEI
    • H01L29/739H01L29/06
    • H01L29/0661H01L29/045H01L29/0615H01L29/0657H01L29/66333H01L29/7395
    • On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.
    • 在薄的半导体晶片的顶表面上形成形成半导体芯片的顶表面结构。 晶片的上表面用双面胶带固定在支撑基板上。 然后,从薄的半导体晶片的底面开始,通过湿式各向异性蚀刻形成成为刻划线的沟槽,使得沟槽的侧壁露出。 在暴露了晶面的沟槽的侧壁上,通过离子注入与底面扩散层的集电极区域同时形成具有不同于用于保持反向击穿电压的半导体晶片的导电类型的隔离层, 然后用激光照射退火。 侧壁形成大致V形或梯形形状的横截面,侧壁相对于支撑基底的角度为30-70°。 然后从上表面去除双面胶带以制造半导体芯片。 通过这样的制造方法,可以形成具有高可靠性的反向阻挡半导体器件。
    • 10. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    • 半导体器件及其形成方法
    • US20100019250A1
    • 2010-01-28
    • US12574805
    • 2009-10-07
    • Shun-Ichi NAKAMURAYoshiyuki YONEZAWA
    • Shun-Ichi NAKAMURAYoshiyuki YONEZAWA
    • H01L29/78H01L29/24H01L21/04
    • H01L29/7813H01L29/0619H01L29/0649H01L29/0657H01L29/0661H01L29/0878H01L29/1608H01L29/4236H01L29/42368H01L29/4238H01L29/66068H01L29/7811
    • A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC. The sidewall surfaces of the trench located below the gate electrode is inclined to form a trapezoidal profile.
    • 半导体器件及其形成方法具有在基板上依次层叠的场阻挡层,漂移层,电流扩展层,体区域和源极接触区域。 提供到达场停止层或基板的沟槽。 栅极电极设置在沟槽中的上半部分中。 在比沟槽中的栅电极的位置更深的部分中,埋入绝缘体的绝缘击穿电场强度的正常值等于或大于绝缘击穿电场强度的绝缘击穿电场强度 基体 由于沟槽底部的绝缘体膜的绝缘击穿,这就抑制了栅极和漏极之间的短路,从而在使用诸如SiC的半导体材料的半导体器件中实现高的击穿电压。 位于栅电极下方的沟槽的侧壁表面倾斜以形成梯形轮廓。