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1. 发明授权

US4490784A High-speed data transfer unit for digital data processing system 失效
标题翻译：数字数据处理系统的高速数据传输单元
公开(公告)号：US4490784A
公开(公告)日：1984-12-25
申请号：US370506
申请日：1982-04-21
申请人： David C. Ives , David K. Miller , Simon Steely, Jr.
发明人： David C. Ives , David K. Miller , Simon Steely, Jr.
IPC分类号： G06F13/28 , G06F13/12 , G06F1/00
CPC分类号： G06F13/122
摘要： A high-speed data transfer unit that transfers data between a central processing unit in a data processing system and an external device such as a disk drive. The transfer unit has two control units, one that controls transfers with the central processing unit under control of port control commands from the processor, and the other that controls transfers with the external device under control of operational commands.
摘要翻译：一种在数据处理系统中的中央处理单元和诸如磁盘驱动器的外部设备之间传送数据的高速数据传送单元。传送单元具有两个控制单元，一个控制单元，一个控制中央处理单元的传输，在来自处理器的端口控制命令的控制下，另一个控制单元在操作命令的控制下控制与外部设备的传输。

2. 发明授权

US5058041A Semaphore controlled video chip loading in a computer video graphics system 失效
标题翻译：信号量控制视频芯片加载在计算机视频图形系统中
公开(公告)号：US5058041A
公开(公告)日：1991-10-15
申请号：US206203
申请日：1988-06-13
申请人： Robert C. Rose , Larry D. Seiler , James L. Pappas
发明人： Robert C. Rose , Larry D. Seiler , James L. Pappas
IPC分类号： G09G5/14 , G09G5/395
CPC分类号： G09G5/395 , G09G5/14
摘要： A method and apparatus for updating the copies of state table values of a video data path chip set for a computer graphics system is provided. The apparatus uses off screen bitmap memory or other dual-ported memory in a frame buffer to store a shadow copy of the state that is stored in the video data path chips. The state tables include such things as color lookup tables, window definitions and cursors. A semaphore is used to prevent screen glitches caused by updating state tables from the copy of state table values that are partially modified. The state tables are loaded into the chips during vertical retrace, when the screen is being blanked. Before the CPU begins to update the shadow copy in the frame buffer, it claims the semaphore. If a vertical retrace occurs before the CPU has completed updating the frame buffer, the chips are not loaded during that vertical retrace. Before the chips start loading, a system timing chip claims the semaphore. The CPU cannot commence modifying the frame buffer until the load is finished.
摘要翻译：提供了一种用于更新计算机图形系统的视频数据路径芯片组的状态表值的副本的方法和装置。该设备使用屏幕位图存储器或帧缓冲器中的其他双端口存储器来存储存储在视频数据路径芯片中的状态的影子副本。状态表包括颜色查找表，窗口定义和光标等。信号量用于防止从部分修改的状态表值的副本更新状态表导致的屏幕故障。当屏幕被消隐时，状态表在垂直回扫期间加载到芯片中。在CPU开始更新帧缓冲区中的卷影副本之前，它会声明信号量。如果在CPU完成更新帧缓冲区之前发生垂直回扫，则在该垂直回扫期间芯片不会被加载。在芯片开始加载之前，系统定时芯片要求信号量。在负载完成之前，CPU无法开始修改帧缓冲区。

3. 发明授权

US06011679A Methods and apparatus for controlling a power supply with improved techniques for providing protection limits 有权
标题翻译：用于提供保护限制的改进技术来控制电源的方法和装置
公开(公告)号：US06011679A
公开(公告)日：2000-01-04
申请号：US163705
申请日：1998-09-30
申请人： William Ng , Bernhard Schroter
发明人： William Ng , Bernhard Schroter
IPC分类号： H02H3/00 , H02H3/20 , H02H7/00 , H02H7/10
CPC分类号： H02H3/202 , H02H3/006
摘要： A technique for controlling a power supply involves receiving a programming signal that indicates a power supply output voltage limit, activating the power supply such that the power supply provides a power supply output voltage according to a power supply threshold voltage, generating a tracking signal that tracks the programming signal, and generating a compare signal according to the tracking signal and an actual value of the power supply output voltage. The technique further involves comparing the compare signal to a protection threshold voltage, maintaining activation of the power supply when the compare signal is less than the protection threshold voltage, and deactivating the power supply when the compare signal is greater than the protection threshold voltage. The protection threshold voltage is independent of the power supply threshold voltage. In particular, a power supply threshold reference source provides the power supply threshold voltage, a protection threshold reference source, which is independent of the power supply threshold reference source, provides the protection threshold voltage.
摘要翻译：一种用于控制电源的技术包括接收指示电源输出电压限制的编程信号，激活电源，使得电源根据电源阈值电压提供电源输出电压，产生跟踪信号编程信号，根据跟踪信号和电源输出电压的实际值产生比较信号。该技术还包括将比较信号与保护阈值电压进行比较，当比较信号小于保护阈值电压时保持电源的激活，以及当比较信号大于保护阈值电压时停用电源。保护阈值电压与电源阈值电压无关。特别地，电源阈值参考源提供电源阈值电压，独立于电源阈值参考源的保护阈值参考源提供保护阈值电压。

4. 发明授权

US5684944A Atomic update of EDC protected data 失效
标题翻译：原子更新EDC保护的数据
公开(公告)号：US5684944A
公开(公告)日：1997-11-04
申请号：US514711
申请日：1995-08-14
申请人： Clark E. Lubbers , Susan G. Elkington
发明人： Clark E. Lubbers , Susan G. Elkington
IPC分类号： G06F11/10 , G11C29/00 , G06F11/00
CPC分类号： G06F11/1044 , G11C29/88
摘要： A method for atomically updating Error Detection Code (EDC) protected data in memory such that the EDC protection is maintained to the granularity of a single microprocessor machine instruction. The method is employed in a memory system having a volatile storage area and at least one nonvolatile storage area, each of the storage areas storing a copy of the protected data and two copies of its associated error detection code. The volatile and nonvolatile storage areas each have a first storage location for storing one of the copies of the associated error code and a second storage location for storing the other of the copies of the associated error code. In such a system, a chosen field with the data structure in the volatile copy is updated. Once the volatile copy is updated, a new error detection code is computed with the data in the volatile copy. The new error detection code is then written to the first storage location in each of the storage areas, volatile and nonvolatile, one at a time. Once the copies have been written with the new EDC, the chosen field of the data structure within the nonvolatile copy is updated. Lastly, the new error code is written to the second storage location in each of the updated storage areas.
摘要翻译：一种用于原子更新存储器中的错误检测码（EDC）保护数据的方法，使得EDC保护被保持为单个微处理器机器指令的粒度。该方法用于具有易失性存储区域和至少一个非易失性存储区域的存储器系统中，每个存储区域存储受保护数据的副本和其相关联的错误检测码的两个副本。易失性和非易失性存储区域各自具有用于存储相关错误代码的副本之一的第一存储位置和用于存储相关联的错误代码的另一副本的第二存储位置。在这样的系统中，更新了具有易失性拷贝中的数据结构的所选字段。一旦更新了易失性拷贝，就会使用易失性拷贝中的数据来计算新的错误检测码。然后，将新的错误检测码写入每个存储区域中的易失性和非易失性存储区域中的第一存储位置，一次一个。一旦使用新的EDC写入了副本，则更新非易失性拷贝中数据结构的选定字段。最后，将新的错误代码写入每个更新的存储区域中的第二存储位置。

5. 发明授权

US5669002A Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory 失效
标题翻译：多处理器资源锁定机制，具有对应于存储在公共存储器中的每个资源的锁定寄存器
公开(公告)号：US5669002A
公开(公告)日：1997-09-16
申请号：US569555
申请日：1995-12-08
申请人： Bruce D. Buch
发明人： Bruce D. Buch
IPC分类号： G06F9/46 , G06F12/02 , G06F12/14 , G06F15/167
CPC分类号： G06F9/52
摘要： A method and apparatus to reduce bus usage and to increase resource locking protocol compatibility within a heterogeneous processing environment. Lock indicators are maintained in stores designated as lock registers and access to a resource is gained by any processor depending upon the status of a lock register associated with that resource. Access to a locked resource is barred to all but the locking processor, and only the processor which has set a lock can use or release that locked resource. A lock register controller controls the contents of the lock registers. A given processor P1-PN is identified by a unique ID vector G1-GN. These vectors are used to indicate both that a resource is locked and to indicate the identity of the locking processor. An unlocked resource is identified by a status vector (G.O slashed.). In a preferred embodiment, acquisition of exclusive access to an available resource is obtained with a simple read command; release of exclusive access is achieved with a simple write executed by the processor which has set the lock. By convention, processors will not access a resource requiring exclusive access until an inquiry of the associated lock register returns the G.O slashed. vector to the inquiring processor.
摘要翻译：一种在异构处理环境中减少总线使用并增加资源锁定协议兼容性的方法和装置。锁定指示器被保存在指定为锁定寄存器的存储器中，并且根据与该资源相关联的锁定寄存器的状态，任何处理器获得对资源的访问。除了锁定处理器之外，对锁定资源的访问被禁止，只有设置了锁定的处理器才能使用或释放锁定的资源。锁定寄存器控制器控制锁定寄存器的内容。给定处理器P1-PN由唯一的ID矢量G1-GN识别。这些向量用于指示资源被锁定并指示锁定处理器的标识。解锁资源由状态向量（G + 527）标识。在优选实施例中，通过简单的读取命令来获得对可用资源的独占访问; 通过已设置锁定的处理器执行的简单写入来实现专用访问的释放。按照惯例，处理器将不会访问需要独占访问的资源，直到相关锁定寄存器的查询将G + 527向量返回给查询处理器。

6. 发明授权

US5481538A Frame removal mechanism for token ring networks using one or more start strip delimiter frames or circulation time interval 失效
标题翻译：使用一个或多个起始条带分隔符帧或循环时间间隔的令牌环网络的帧去除机制
公开(公告)号：US5481538A
公开(公告)日：1996-01-02
申请号：US866958
申请日：1992-04-09
申请人： Henry S. Yang , K. K. Ramakrishnan , Barry Spinney
发明人： Henry S. Yang , K. K. Ramakrishnan , Barry Spinney
IPC分类号： H04L12/433 , H04L12/46
CPC分类号： H04L12/4637 , H04L12/433
摘要： Frame processing apparatus, and a related method for its operation, for use in a station connected to a token ring network, to ensure rapid stripping of frames from the network without reference to source addresses in the frames, and in spite of the possible presence of extraneous no-owner frames on the network. The adverse effects of extraneous no-owner frames are avoided by any of three techniques. First, transmitted information frames are preceded by a start strip delimiter frame and followed by an end strip delimiter frame. The process strips all incoming frames (except tokens and ring initialization frames, which are specially handled), but does not count the stripped frames until the start strip delimiter frame is detected. Therefore, extraneous frames preceding the transmitted information frames will be stripped but not counted, and all of the transmitted frames will be stripped. In another approach, an estimated stripping time is used to terminate stripping. Frame counters are not then needed and extraneous frames will be stripped prior to the desired information frames. A third approach is to preset the transmitted frame count to some selected value, so that more frames will be stripped than were transmitted. Thus, preceding extraneous frames will be stripped, but the end strip delimiter will still terminate stripping and preclude overstripping.
摘要翻译：帧处理装置及其操作的相关方法，用于连接到令牌环网络的站，以确保帧的快速剥离，而不参考帧中的源地址，并且尽管可能存在无线网络上的无人机框架。通过三种技术中的任何一种避免了外来的非所有权框架的不利影响。首先，发送的信息帧之前是开始条带分隔符帧，后跟一个结束条带分隔符帧。该进程将剥离所有传入的帧（除特殊处理的令牌和环初始化帧外），但在检测到起始条带定界符帧之前不计算剥离的帧。因此，发送的信息帧之前的外部帧将被剥离但不被计数，并且所有发送的帧将被剥离。在另一种方法中，使用估计的剥离时间来终止剥离。然后不需要帧计数器，并且在所需信息帧之前将剥离无关帧。第三种方法是将发送的帧计数预设为某些选定的值，以便比传输更多的帧被剥离。因此，以前的外部框架将被剥离，但是终端条带分隔符将仍然终止剥离并排除超标。

7. 发明授权

US5471404A Occlusion detection system for locator devices 失效
标题翻译：定位装置遮挡检测系统
公开(公告)号：US5471404A
公开(公告)日：1995-11-28
申请号：US173437
申请日：1993-12-23
申请人： Murray S. Mazer
发明人： Murray S. Mazer
IPC分类号： G01S13/86 , G01S13/87 , G01S17/87 , G07C9/00 , G08B3/10 , G01S3/02
CPC分类号： G08B3/1083 , G01S13/878 , G07C9/00111 , G01S13/86 , G01S17/87
摘要： A system to enable individual locator devices or badges developed for location of people or objects to (1) determine whether their identification transmissions are received by sensor stations and to (2) take appropriate actions when the transmissions are not received. Each badge in the system can transmit to any sensor station in the system a request for an acknowledgement within a set interval of time. Each time a sensor station receives a request for acknowledgement from a badge the sensor station sends a message of acknowledgement to the badge. If the badge does not receive an acknowledgement within the set interval of time, the badge takes appropriate action due to its occlusion from the system. If the badge receives an acknowledgement within the interval of time, it resets its internal timer.
摘要翻译：一种用于为个人或物体的位置而开发的个体定位装置或徽章的系统，用于（1）确定它们的识别传输是否被传感器站接收，以及（2）当没有接收到传输时采取适当的动作。系统中的每个徽章可以在设定的时间间隔内向系统中的任何传感器站传送确认请求。每当传感器站接收到来自徽章的确认请求时，传感器站向徽章发送确认消息。如果徽章在设定的时间间隔内没有收到确认，则徽章由于其从系统中的遮挡而采取适当的动作。如果徽章在时间间隔内收到确认，则会重置其内部定时器。

8. 发明授权

US5453983A Port controller 失效
标题翻译：端口控制器
公开(公告)号：US5453983A
公开(公告)日：1995-09-26
申请号：US130609
申请日：1993-10-01
申请人： Anne O'Connell , John Hickey , Tadhg Creedon
发明人： Anne O'Connell , John Hickey , Tadhg Creedon
IPC分类号： G06F13/362 , G06F13/18 , G06F13/376 , H04J3/17
CPC分类号： G06F13/362
摘要： Two devices HR and FR are coupled to a bus with a common memory via a port controller. Device HR requires a high (or maximum) average rate of access, device FR requires a fast response (minimum latency) in establishing access. Request signals HRQ, FRQ from the devices are latched by latches 20 and 21, passed as HRX, FRX through an arbitration or resolver circuit 22 as HRY, FRY to a sequence control unit 23 to initiate an access cycle. Cycle timing is determined by a delay line timebase circuit 24, which responds to a single change of level of a signal DLY (in either direction). Latch 21, when set, generates an request pending signal FRRP which is fed to the HR device to cause it to increase its cycle length so that the FR access cycle will finish before the next HR access cycle is initiated.
摘要翻译：两个设备HR和FR通过端口控制器耦合到具有公共存储器的总线。设备HR需要高（或最大）平均访问速率，设备FR需要在建立访问时的快速响应（最小延迟）。来自装置的请求信号HRQ，FRQ由锁存器20和21锁存，通过作为HRY，FRY的仲裁或解析器电路22作为HRX，FRX传递到序列控制单元23以启动访问周期。周期定时由延迟线时基电路24确定，延迟线时基电路24响应于信号DLY（在任一方向上）的电平的单次改变。锁存器21当被设置时产生请求等待信号FRRP，其被馈送到HR设备以使其增加其周期长度，使得FR访问周期将在下一个HR访问周期启动之前完成。

9. 发明授权

US5367705A In-register data manipulation using data shift in reduced instruction set processor 失效
标题翻译：在精简指令集处理器中使用数据移位的寄存器数据操作
公开(公告)号：US5367705A
公开(公告)日：1994-11-22
申请号：US117482
申请日：1993-09-07
申请人： Richard L. Sites , Richard T. Witek
发明人： Richard L. Sites , Richard T. Witek
IPC分类号： G06F9/30 , G06F9/308 , G06F9/312 , G06F9/38 , G06F9/00 , G06F12/00
CPC分类号： G06F12/1027 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30054 , G06F9/30072 , G06F9/30087 , G06F9/3816 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F2212/652
摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing inregister byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.
摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。包括允许使用以前建立的数据结构的字节操作指令包括用于执行字节提取，插入和屏蔽以及非对齐加载和存储指令的功能。提供加载/锁定和存储/条件指令允许实现原子字节写入。

10. 外观设计

USD350341S Display monitor 失效
公开(公告)号：USD350341S
公开(公告)日：1994-09-06
申请号：US6094
申请日：1993-03-16
申请人： Christian C. Landry
设计人： Christian C. Landry

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