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1. 发明授权

US4852171A Apparatus and method for speech recognition 失效
标题翻译：用于语音识别的装置和方法
公开(公告)号：US4852171A
公开(公告)日：1989-07-25
申请号：US670521
申请日：1984-11-09
申请人： Priyadarshan Jakatdar , Hoshang D. Mulla
发明人： Priyadarshan Jakatdar , Hoshang D. Mulla
IPC分类号： G10L11/00 , G10L15/06 , G10L15/10
CPC分类号： G10L15/063
摘要： A template-matching speech recognition system has a plurality of reference templates each having a plurality of addressable positions, each position storing a value corresponding to the probability of the occurrence of a particular binary value in a corresponding position in an utterance template for speech represented by the referenced template. A system bias template having a corresponding plurality of positions for storing values therein that are representative of the probability of the particular binary value occurring in a corresponding position of any utterance template. A match between an utterance template and a reference template is determined when the sum of the stored probabilities from the reference template positions, corresponding to the positions in the utterance template containing the particular binary value, exceed a predetermined threshold.
摘要翻译：模板匹配语音识别系统具有多个参考模板，每个参考模板具有多个可寻址位置，每个位置存储与用于语音的话语模板中的对应位置中出现特定二进制值的概率相对应的值，引用的模板。一种系统偏置模板，具有对应的多个位置，用于存储其中的值，其代表在任何话语模板的对应位置中出现特定二进制值的概率。当与包含特定二进制值的话语模板中的位置相对应的参考模板位置存储的概率的总和超过预定阈值时，确定话语模板和参考模板之间的匹配。

2. 发明授权

US4835729A Single instruction multiple data (SIMD) cellular array processing apparatus with on-board RAM and address generator apparatus 失效
标题翻译：具有板载RAM和地址发生器装置的单指令多数据（SIMD）蜂窝阵列处理装置
公开(公告)号：US4835729A
公开(公告)日：1989-05-30
申请号：US808314
申请日：1985-12-12
申请人： Steven G. Morton
发明人： Steven G. Morton
IPC分类号： G06F15/16 , G01R31/3185 , G06F11/20 , G06F15/80 , G11C29/28
CPC分类号： G06F11/2051 , G01R31/318505 , G06F15/8007 , G11C29/28
摘要： In a cellular array processor at least two of the plurality of processors in a row cooperate together as an address generator so that large amounts of memory external to the array chip may be addressed and in addition so that an address . may be generated onboard for use by the DRAM memory associated with each processor. Based on this structure, a memory with an internal organization that is 256-bits wide may be connected to 16 16-bit processors which would require 256 bits of data. In so doing, a vast number of pins are saved, that is 256 bits of data out of the memory and 256 bits of data into the processing cells by combining the processing cells and memory on the same chip. It is significant that exactly one design of a processing cell may provide both a data processing element and an address processing element. In this way, these cells are interchangeable to maximize the yield and reliability of the device. A single address from the address generator addresses the entire onboard DRAM so as to use the number of address generators required and to reduce the amount of address decode logic required as well as minimizing power dissipation in the DRAM portion of the chip.
摘要翻译：在蜂窝阵列处理器中，一行中的多个处理器中的至少两个处理器作为地址发生器协同工作，使得可以寻址阵列芯片外部的大量存储器，并且另外地址使得地址。可以在板上生成以供与每个处理器相关联的DRAM存储器使用。基于这种结构，具有256位宽的内部组织的存储器可以连接到需要256位数据的16位16位处理器。这样做，通过将处理单元和存储器组合在同一芯片上，大量的引脚被保存在存储器中的256位数据和256位数据到处理单元中。重要的是，处理单元的恰好一个设计可以提供数据处理元件和地址处理元件。以这种方式，这些电池可以互换，以最大限度地提高设备的产量和可靠性。来自地址生成器的单个地址解决整个板载DRAM，以便使用所需的地址生成器的数量，并且减少所需的地址解码逻辑的数量以及最小化芯片的DRAM部分中的功耗。

3. 发明授权

US4821319A Single line telephone communication system 失效
标题翻译：单线电话通讯系统
公开(公告)号：US4821319A
公开(公告)日：1989-04-11
申请号：US47586
申请日：1987-05-05
申请人： Francisco A. Middleton , David A. Zeller, Jr.
发明人： Francisco A. Middleton , David A. Zeller, Jr.
IPC分类号： H04M1/723 , H04M9/02 , H04M3/56
CPC分类号： H04M9/02 , H04M1/723
摘要： A communication system for use with a single pair of externally provided telephone wires and a single pair of in-house wires for the provision of full intercom services and/or PABX type features to a plurality of subsets includes a line interface module connected between the single pair of externally supplied wires and a single pair of in-house wires. In addition, each subset is provided with a station adapter module between it and the single pair of in-house wires.
摘要翻译：用于与一对外部提供的电话线和用于向多个子集提供全对讲服务和/或PABX类型特征的单对内部线路的通信系统包括连接在单个电话线之间的线路接口模块一对外部电源线和一对内部电线。此外，每个子集在其与单对内部线之间设置有站适配器模块。

4. 发明授权

US4790625A Method of applying hermetic coating on optical fiber 失效
标题翻译：在光纤上应用气密涂层的方法
公开(公告)号：US4790625A
公开(公告)日：1988-12-13
申请号：US88547
申请日：1987-08-20
申请人： Dipak R. Biswas , Satyabrata Raychaudhuri
发明人： Dipak R. Biswas , Satyabrata Raychaudhuri
IPC分类号： C03C25/10 , C03C25/22 , C23C16/48 , G02B6/10 , G02B6/22 , G02B6/00
CPC分类号： C03C25/108 , C03C25/104 , C03C25/107 , C03C25/223 , C23C16/481
摘要： An optical fiber which has just been drawn from an optical preform is provided with two external hermetic coatings. The primary coating is a metallic or dielectric coating provided by, for example, using a heterogeneous nucleation thermochemical deposition (HNTD) technique. This technique involves passing the fiber through a reaction zone which contains a gaseous medium that includes a reactant which decomposes, or a mixture of reactants which chemically react, at a predetermined temperature, to form the material of the coating. Such predetermined temperature is available from the heat of the fiber forming process which is retained at the fiber surface by means of a shielding element so that additional heating means is not required. The second coating may be deposited, by for example, using an HNTD or a chemical vapor deposition process. The resulting fiber may then be provided with an additional polymer coating layer.
摘要翻译：刚刚从光学预型件中拉出的光纤设置有两个外部密封涂层。初级涂层是通过例如使用异相成核热化学沉积（HNTD）技术提供的金属或电介质涂层。该技术涉及使纤维通过含有气态介质的反应区，该反应区包含分解的反应物或在预定温度下化学反应的反应物的混合物以形成涂层的材料。这样的预定温度可以通过纤维形成工艺的热量获得，其通过屏蔽元件保持在纤维表面，使得不需要额外的加热装置。可以通过例如使用HNTD或化学气相沉积工艺来沉积第二涂层。然后可以向所得纤维提供另外的聚合物涂层。

5. 发明授权

US4918597A Adaptive interface for transferring segmented message between device and microcomputer on line division multiplexed bus 失效
标题翻译：用于在线路复用总线上在设备和微机之间传送分段消息的自适应接口
公开(公告)号：US4918597A
公开(公告)日：1990-04-17
申请号：US682035
申请日：1984-12-14
申请人： Iyengar N. Krishnan , Herbert J. Toegel
发明人： Iyengar N. Krishnan , Herbert J. Toegel
IPC分类号： G06F13/38 , G06F13/12 , G06F13/20 , H04Q11/04
CPC分类号： H04Q11/0407 , G06F13/20
摘要： An interface for use with a microcomputer is provided with memory that in one operating mode is used as a first-in first-out buffer, and in a second operating mode allows the direct data transfer across the interface. The interface also includes a means for selecting the operating mode thereof.
摘要翻译：与微型计算机一起使用的接口提供有在一个操作模式中被用作先进先出缓冲器的存储器，并且在第二操作模式中允许跨接口的直接数据传输。接口还包括用于选择其操作模式的装置。

6. 发明授权

US4916657A Single instruction multiple data (SIMD) cellular array processing apparatus employing multiple state logic for coupling to data buses 失效
标题翻译：单指令多数据（SIMD）蜂窝阵列处理装置采用多状态逻辑耦合到数据总线
公开(公告)号：US4916657A
公开(公告)日：1990-04-10
申请号：US808315
申请日：1985-12-12
申请人： Steven G. Morton
发明人： Steven G. Morton
IPC分类号： G06F15/16 , G01R31/3185 , G06F11/20 , G06F15/80
CPC分类号： G06F11/2051 , G01R31/318505 , G06F15/8007
摘要： A cellular array having a plurality of processor cells disposed on a chip and interconnected by an internal bus includes data bus couplers for bidirectionally coupling to one or more external buses. The data bus couplers selectively couple buses having multiple logic levels. The number of logic levels on the coupled buses may differ. The internal bus may comprise a plurality of parallel data lines each having two-level logic such as binary data, whereas the external buses may have four-level logic represented by four voltage levels. Each data bus coupler has two-bit A/D and D/A converters parallelly connected to selectively convert two bits of two-level logic data to multiple level data and vice versa. The data bus coupler also has a logic level selector circuit using bidirectional gates for selective operation between buses having similar or dissimilar logic levels. The data bus couplers may be associated with pins organized in a regular architecture and used in connection with bedirectional transceivers to multiplex data corresponding to a multiplicity of external buses onto the internal bus and vice versa. Using this pin architecture the data bus couplers may be dynamically configured to support a collection of two-level and four-level external buses to suit the interfacing needs of the chip.
摘要翻译：具有设置在芯片上并由内部总线互连的多个处理器单元的蜂窝阵列包括用于双向耦合到一个或多个外部总线的数据总线耦合器。数据总线耦合器选择性地耦合具有多个逻辑电平的总线。耦合总线上的逻辑电平数量可能不同。内部总线可以包括多个并行数据线，每条并行数据线具有诸如二进制数据的二级逻辑，而外部总线可以具有由四个电压电平表示的四电平逻辑。每个数据总线耦合器具有并行连接的两位A / D和D / A转换器，以选择性地将两级二级逻辑数据转换为多级数据，反之亦然。数据总线耦合器还具有使用双向门的逻辑电平选择器电路，用于具有相似或不相似逻辑电平的总线之间的选择性操作。数据总线耦合器可以与以常规架构组织的引脚相关联，并且与双向收发器结合使用以将对应于多个外部总线的数据复用到内部总线上，反之亦然。使用该引脚架构，数据总线耦合器可以动态地配置为支持两级和四级外部总线的集合，以适应芯片的接口需求。

7. 外观设计

USD299132S Combined telephone handset and stand 失效
公开(公告)号：USD299132S
公开(公告)日：1988-12-27
申请号：US805014
申请日：1985-12-05
申请人： James T. Asaki , Robert L. Gault
设计人： James T. Asaki , Robert L. Gault

8. 发明授权

US4782480A Telephone line access apparatus 失效
标题翻译：电话线路接入设备
公开(公告)号：US4782480A
公开(公告)日：1988-11-01
申请号：US799522
申请日：1985-11-19
申请人： Franklin Hargrave , Francisco A. Middleton , David A. Zeller, Jr.
发明人： Franklin Hargrave , Francisco A. Middleton , David A. Zeller, Jr.
IPC分类号： H03H9/54 , H03H9/60 , H04M3/00 , H04M3/18 , H04M11/06 , H04Q1/14 , H04J1/14
CPC分类号： H04M11/062 , H03H9/60 , H04M3/005 , H04M3/007 , H04M3/18 , H04Q1/14
摘要： A telephone line access apparatus includes a first stage for providing high voltage protection and a second stage filter in series with the first stage. The first and second stages are incorporated within a housing that is adapted to plug into an existing main distribution frame of a telephone central office.
摘要翻译：电话线接入装置包括用于提供高电压保护的第一级和与第一级串联的第二级滤波器。第一和第二阶段结合在适于插入电话中心局的现有主分配框架的壳体内。

9. 发明授权

US4780842A Cellular processor apparatus capable of performing floating point arithmetic operations 失效
标题翻译：能进行浮点运算的蜂窝处理装置
公开(公告)号：US4780842A
公开(公告)日：1988-10-25
申请号：US844395
申请日：1986-03-26
申请人： Steven G. Morton , Enrique J. Abreu
发明人： Steven G. Morton , Enrique J. Abreu
IPC分类号： G06F7/57 , G06F11/00 , G06F15/80 , G06F7/38 , G06F13/00
CPC分类号： G06F7/483 , G06F15/8023 , G06F2207/3856 , G06F2207/3896 , G06F7/4991 , G06F7/49936 , G06F7/49947
摘要： A processor apparatus which is capable of performing floating point arithmetic. The processor apparatus includes a plurality of individual processing cells which are interconnected from left to right in a chain so that any of the processor cells can operate to receive a bit of any slice in a digital word. Each cell includes a memory which essentially is coupled via a multiplexer to an arithmetic logic unit, a controllable multiplier quotient store, a controllable loop path, and controllable status path device. Each of these devices are under control of a control mechanism which is included in the cell, and therefore each path can be connected to any other path via various multiplexers utilized in the circuitry. Essentially, each cell includes a multiport RAM, programmable logic arrays which implement the control logic plus path logic which provides the communication between neighboring cells. In order to command a particular 1-bit processor to perform as a particular bit in a floating point word, a multiplicity of slice types is defined. Hence the floating point implementation requires 15 slice types to handle all different combinations of bit operations that must be performed. The logic is such that defective 1-bit processors appear invisible so that data can flow across them without interference. The cell is a relatively unified structure whereby each cell can be thus commanded to perform a particular operation on a particular slice of a given word independent of the operation of any other cell.
摘要翻译：一种能够进行浮点运算的处理器装置。处理器装置包括多个单独处理单元，它们在链中从左到右互连，使得处理器单元中的任何一个可以操作以接收数字字中的任何切片的位。每个单元包括基本上通过多路复用器耦合到算术逻辑单元，可控乘法器商存储器，可控环路径和可控状态路径设备的存储器。这些设备中的每一个都在被包括在单元中的控制机构的控制下，并且因此每个路径可以经由在电路中使用的各种多路复用器连接到任何其他路径。本质上，每个单元包括多端口RAM，其实现了提供相邻单元之间的通信的控制逻辑加路径逻辑的可编程逻辑阵列。为了命令特定的1位处理器作为浮点字中的特定位执行多个片类型的定义。因此，浮点实现需要15个片类型来处理必须执行的位操作的所有不同组合。逻辑是这样的，有缺陷的1位处理器看起来是不可见的，因此数据可以跨越它们而不受干扰。该小区是相对统一的结构，由此可以使每个小区被命令对独立于任何其他小区的操作的给定单词的特定切片执行特定操作。

10. 发明授权

US4922416A Interface device end message storing with register and interrupt service registers for directing segmented message transfer between intelligent switch and microcomputer 失效
标题翻译：接口设备结束消息存储与寄存器和中断服务寄存器，用于指示智能开关和微型计算机之间的分段消息传输
公开(公告)号：US4922416A
公开(公告)日：1990-05-01
申请号：US682034
申请日：1984-12-14
申请人： Iyengar N. Krishnan , Herbert J. Toegel
发明人： Iyengar N. Krishnan , Herbert J. Toegel
IPC分类号： G06F13/28 , G06F13/40 , H04Q3/545
CPC分类号： G06F13/404 , G06F13/28 , H04Q3/54516 , H04Q2213/1305 , H04Q2213/13109 , H04Q2213/13376
摘要： An interface for effecting the direct transfer of message segments between an intelligent switch and a microcomputer includes an input buffer, an output buffer and a memory for storing address to be associated with the message segments traversing the buffers.
摘要翻译：用于实现智能开关和微计算机之间的消息段的直接传送的接口包括输入缓冲器，输出缓冲器和用于存储与遍历缓冲器的消息段相关联的地址的存储器。

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