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1. 发明授权

US09580792B2 Shadow mask alignment using variable pitch coded apertures 有权
标题翻译：使用可变间距编码孔的阴影掩模对准
公开(公告)号：US09580792B2
公开(公告)日：2017-02-28
申请号：US14812076
申请日：2015-07-29
申请人： ADVANTECH GLOBAL, LTD
发明人： Nobuhiko Tamura
IPC分类号： G01B11/00 , C23C14/04 , C23C16/04 , G01B11/27 , G02B27/30
CPC分类号： C23C14/042 , C23C16/042 , G01B11/27 , G02B27/30
摘要： In a shadow mask-substrate alignment method, a substrate and a shadow mask each include a grate having a plurality of bars in spaced relation, wherein for each grate, each pair of spaced bars of each grate is separated by a gap. The spacing between at least three adjacent gaps is different or not of constant pitch, and at least one grate includes a gap that extends therethrough. The grate of the substrate and the grate of the shadow mask are positioned in a light path. Thereafter, the orientation of the substrate, the shadow mask, or both are caused to be adjusted to position the grate of the substrate, the grate of the shadow mask, or both until a predetermined amount of light or range of an amount of light on the light path passing through one or both of the grates is received by a light receiver.
摘要翻译：在阴影掩模 - 衬底对准方法中，衬底和荫罩各自包括具有间隔开的多个条的格栅，其中对于每个格栅，每个格栅的每对隔开的条被间隔开。至少三个相邻间隙之间的间距是不同的或不是恒定的间距，并且至少一个格栅包括延伸穿过其中的间隙。衬底的格栅和荫罩的格栅位于光路中。然后，调整基板，荫罩或两者的取向，使基板的格栅，荫罩的格栅或两者均匀，直到预定量的光量或光量范围通过一个或两个格栅的光路由光接收器接收。

2. 发明申请

US20140325822A1 Method and Apparatus for Tensioning a Shadow Mask for Thin Film Deposition 有权
标题翻译：用于张贴薄膜沉积阴影掩模的方法和装置
公开(公告)号：US20140325822A1
公开(公告)日：2014-11-06
申请号：US14265773
申请日：2014-04-30
申请人： ADVANTECH GLOBAL, LTD
发明人： Brian Arthur Bucci
IPC分类号： B05B15/04
CPC分类号： G03F7/70733 , B05B12/20 , B05B12/24 , B05B12/29 , C23C14/04 , C23C14/042 , H01J29/073 , H01J2229/07 , H01J2229/0705 , H01J2229/0711 , H01J2229/0716 , H01J2229/0722 , H01J2229/0727 , Y10T29/49867 , Y10T29/53957 , Y10T29/53961
摘要： In a method and apparatus for shadow mask tensioning, a shadow mask frame and an anchor frame are positioned in spaced relation defining a gap therebetween and a shadow mask is positioned on the shadow mask frame and the anchor frame with an interior portion of the shadow mask extending across the gap. An edge of the shadow mask is affixed to the anchor frame and the shadow mask is tensioned by urging the interior portion of the shadow mask into the gap. Once the shadow mask has been tensioned to a desired extent, the shadow mask is affixed to the shadow mask frame. Thereafter, the combination of the shadow mask affixed to the shadow mask frame is separated from the anchor frame.
摘要翻译：在用于荫罩张紧的方法和装置中，荫罩框架和锚定框架以间隔开的关系定位，在其间限定了间隙，并且荫罩位于荫罩框架上，并且锚框架与荫罩的内部部分跨越差距。阴影掩模的边缘固定在锚框上，并且通过将荫罩的内部部分推到间隙中来将荫罩张紧。一旦荫罩被张紧到期望的程度，荫罩就固定在荫罩框架上。此后，固定在荫罩框架上的荫罩的组合与锚架分离。

3. 发明申请

US20120074471A1 Transistor Structure for Improved Static Control During Formation of the Transistor 有权
标题翻译：晶体管形成过程中改善静电控制的晶体管结构
公开(公告)号：US20120074471A1
公开(公告)日：2012-03-29
申请号：US12888723
申请日：2010-09-23
申请人： Timothy A. Cowen
发明人： Timothy A. Cowen
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1225 , H01L29/78681
摘要： A method of forming a shadow mask vapor deposited transistor includes shadow mask vapor depositing a semiconductor segment. An electrically conductive drain contact is shadow mask vapor deposited on a first part of the semiconductor segment and a first insulator is shadow mask vapor deposited on the drain contact. An electrically conductive source contact is shadow mask vapor deposited on a second part of the semiconductor segment spaced from the drain contact and a second insulator is shadow mask vapor deposited on the source contact. A third insulator is shadow mask vapor deposited over at least part of each of the first and second insulators and the semiconductor segment between the drain contact and the source contact. An electrically conductive gate contact is shadow mask vapor deposited on the third insulator and in spaced relation to the semiconductor segment between the drain contact and the source contact.
摘要翻译：形成荫罩气相沉积晶体管的方法包括荫罩蒸镀沉积半导体段。导电漏极接触是沉积在半导体段的第一部分上的阴影掩模，第一绝缘体是沉积在漏极接触上的阴影掩模。导电源接触是沉积在与漏极接触部分隔开的半导体段的第二部分上的阴影掩模，第二绝缘体是沉积在源极接触上的阴影掩模。第三绝缘体是沉积在第一绝缘体和第二绝缘体中的每一个的至少一部分上的阴影掩模和漏极接触件和源极接触件之间的半导体段。导电栅极触点是沉积在第三绝缘体上的阴影掩模，并且与漏极触点和源极触点之间的半导体段间隔开。

4. 发明申请

US20090199968A1 Method and Apparatus for Electronic Device Manufacture Using Shadow Masks 有权
标题翻译：使用阴影掩模制造电子设备的方法和装置
公开(公告)号：US20090199968A1
公开(公告)日：2009-08-13
申请号：US12424873
申请日：2009-04-16
申请人： Thomas Peter Brody
发明人： Thomas Peter Brody
IPC分类号： C23F1/08 , C23C16/54
CPC分类号： C23C14/042 , B08B7/0035 , B08B13/00 , C23C14/564 , H01L27/1214 , H01L27/1288 , H01L29/78681 , H01L51/0011
摘要： Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.
摘要翻译：电子器件形成在通过多个沉积容器逐步前进的衬底上。每个沉积容器包括沉积材料源并且具有与其相关联的至少两个荫罩。两个掩模中的每一个交替地位于相应的沉积容器内，用于通过位于其中的掩模中的孔将沉积材料图案化到衬底上，并且定位在邻近的清洁容器中以进行掩模清洁。同时执行图案化到基板上以及清洁至少一个掩模。

5. 发明申请

US20090151630A1 TENSIONED APERTURE MASK AND METHOD OF MOUNTING 审中-公开
标题翻译：张力防护面罩和安装方法
公开(公告)号：US20090151630A1
公开(公告)日：2009-06-18
申请号：US12299531
申请日：2006-11-01
申请人： Joseph A. Marcanio , Jeffrey W. Conrad
发明人： Joseph A. Marcanio , Jeffrey W. Conrad
IPC分类号： B29C65/02 , B05C11/00
CPC分类号： C23C14/042 , H05K3/1225 , H05K2201/068 , H05K2203/0169 , H05K2203/1105
摘要： In a method of preparing and using an aperture mask, a temperature of an aperture mask is increased to a first, mounting temperature (T1), whereupon the size of the aperture mask increases according to its coefficient of thermal expansion (CTEam), until at least one dimension thereof is of a first desired extent. The temperature of a frame is also increased to T1, whereupon the size of the frame grows according to its coefficient of thermal expansion (CTEf), which is lower than CTEam. The aperture mask is fixedly mounted to the frame at T1. The frame mounted aperture mask is then used for depositing a material on a substrate at a deposition temperature T2 that is less than T1, whereupon the frame holds the shadow mask in tension with the one dimension at a second desired extent.
摘要翻译：在制备和使用孔径掩模的方法中，孔径掩模的温度增加到第一安装温度（T1），于是孔径掩模的尺寸根据其热膨胀系数（CTEam）而增加，直到在其至少一个维度具有第一期望的程度。框架的温度也增加到T1，因此，框架的尺寸根据其低于CTEam的热膨胀系数（CTEf）而增长。光圈掩模在T1固定安装到框架上。然后将框架安装的孔径掩模用于在小于T1的沉积温度T2下将材料沉积在基板上，于是该框架以相反的尺寸在一个维度上保持荫罩的张力。

6. 发明申请

US20090089997A1 Method Of Forming An Electrical Circuit With Overlaying Integration Layer 有权
标题翻译：用叠层集成层形成电路的方法
公开(公告)号：US20090089997A1
公开(公告)日：2009-04-09
申请号：US11868640
申请日：2007-10-08
申请人： Thomas Peter Brody
发明人： Thomas Peter Brody
IPC分类号： H01R43/00 , H05K3/36
CPC分类号： H05K3/28 , H05K3/143 , H05K3/4647 , H05K3/467 , H05K2201/09881 , H05K2203/025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155
摘要： In a method of forming an electrical circuit assembly, a substrate is provided including a plurality of first segments that form an electrical circuit. The first segments have surfaces that rise above surfaces of other segments that form the electrical circuit. All of the segments are deposited on the substrate via one or more shadow mask vapor deposition processes in a vacuum. A photoresist caused to cover all of the segments is hardened and then abraded until surfaces of the first segments are exposed, but surfaces of the other segments are not exposed, and a surface of the abraded photoresist is at the same level as the exposed surfaces of the first segments. Second segments can be deposited on the exposed surfaces of the first segments via a shadow mask vapor deposition process in a vacuum to a level above the top surface of the abraded photoresist.
摘要翻译：在形成电路组件的方法中，提供了包括形成电路的多个第一段的衬底。第一段具有在形成电路的其他段的表面上方的表面。所有的片段通过真空中的一个或多个荫罩气相沉积工艺沉积在衬底上。导致覆盖所有片段的光致抗蚀剂被硬化，然后磨损直到第一片段的表面露出，但是其它片段的表面不被暴露，并且磨损的光致抗蚀剂的表面处于与暴露的表面相同的水平第一段。第二段可以通过在真空中的荫罩气相沉积工艺在第一段的暴露表面上沉积到磨损光致抗蚀剂的顶表面上方的水平。

7. 发明申请

US20080043475A1 System and method for total light extraction from flat-panel light-emitting devices 失效
标题翻译：从平板发光装置全光提取的系统和方法
公开(公告)号：US20080043475A1
公开(公告)日：2008-02-21
申请号：US11812753
申请日：2007-06-21
申请人： Jan Bernkopf
发明人： Jan Bernkopf
IPC分类号： F21V5/00
CPC分类号： H01J61/025 , B82Y20/00 , G02B1/007 , H01J65/046 , H01J2211/44 , H01L51/5262 , H01L51/5275
摘要： A system and method for improving light extraction from luminescent devices such as light-emitting flat-panel displays (for example, light-emitting diode (OLED) flat-panel displays) or flat panel lamps. The system includes a material with negative index of refraction, preferably with n=−1. The presence of such material on the exit surface of the electro-optic devices such as flat panel display or lamp with light-generating medium sandwiched between materials with refractive index n>1 fully removes TIR and results in light outcoupling efficiency of about 100%.
摘要翻译：一种用于改善发光装置如发光平板显示器（例如，发光二极管（OLED）平板显示器）或平板灯的光提取的系统和方法。该系统包括具有负折射率的材料，优选n = -1。在诸如平板显示器或具有折射率n> 1的材料之间的光产生介质的电光装置的出射表面上的这种材料的存在完全去除TIR并导致约100％的光耦合效率。

8. 发明申请

US20080042543A1 Multiple shadow mask structure for deposition shadow mask protection and method of making and using same 审中-公开
标题翻译：用于沉积阴影掩模保护的多重荫罩结构及其制作和使用方法
公开(公告)号：US20080042543A1
公开(公告)日：2008-02-21
申请号：US11900087
申请日：2007-09-10
申请人： Jeffrey Conrad
发明人： Jeffrey Conrad
IPC分类号： H01J29/70
CPC分类号： C23C14/042
摘要： The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask which would cause the deposition mask to deform.
摘要翻译：本发明是一种多层荫罩及其使用方法。多层荫罩包括结合到沉积掩模的牺牲掩模。牺牲掩模提供防止沉积掩模上的蒸发剂积聚的保护，这将使沉积掩模变形。

9. 发明授权

US07271111B2 Shadow mask deposition of materials using reconfigurable shadow masks 有权
公开(公告)号：US07271111B2
公开(公告)日：2007-09-18
申请号：US11147508
申请日：2005-06-08
申请人： Thomas P. Brody
发明人： Thomas P. Brody
IPC分类号： H01L23/31 , C23C16/00
CPC分类号： H01L27/1288 , C23C14/042 , C23C14/562 , H01L27/1214 , H01L27/14683 , Y10S438/944
摘要： A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

10. 发明申请

US20060281206A1 Shadow mask deposition of materials using reconfigurable shadow masks 有权
标题翻译：使用可重构阴影掩模的材料的阴影掩模沉积
公开(公告)号：US20060281206A1
公开(公告)日：2006-12-14
申请号：US11147508
申请日：2005-06-08
申请人： Thomas Brody
发明人： Thomas Brody
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , C23C14/042 , C23C14/562 , H01L27/1214 , H01L27/14683 , Y10S438/944
摘要： A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.
摘要翻译：阴影掩模沉积系统包括多个相同的阴影掩模，其布置在多个堆叠中以形成相同数量的复合荫罩，每个复合荫罩与材料沉积源一起设置在沉积真空容器中。来自材料沉积源的材料通过相应的复合阴影掩模中的开口沉积在基板上，每个开口由形成复合荫罩的阴影掩模中的孔的整体或部分对准形成，以形成电子元件阵列基质。

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