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1. 发明申请

US20020019924A1 Flexible processing hardware architecture 有权
标题翻译：灵活的处理硬件架构
公开(公告)号：US20020019924A1
公开(公告)日：2002-02-14
申请号：US09977413
申请日：2001-10-15
申请人： Acuity Imaging, LLC
发明人： David C. Davies , Michael P. Greenberg , Michael J. Wilt , John E. Agapakis
IPC分类号： G06F015/00 , G06F015/76
CPC分类号： G06F13/4027 , G06T1/60 , G06T5/20
摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory apace allocated to the surrogate card by the BIOS.
摘要翻译：灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接夹层式连接器，并插入个人计算机PCI扩展槽。该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。主系统BIOS将读取类代码，并根据代理卡预留内存。非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的内存空间。

2. 发明授权

US5977994A Data resampler for data processing system for logically adjacent data samples 失效
标题翻译：用于逻辑相邻数据样本的数据处理系统的数据重采样器
公开(公告)号：US5977994A
公开(公告)日：1999-11-02
申请号：US25938
申请日：1998-02-19
申请人： Michael P. Greenberg , Michael J. Wilt
发明人： Michael P. Greenberg , Michael J. Wilt
IPC分类号： G06F13/40 , G06F15/00 , G06T1/20 , G06T1/60 , G06T3/40 , G06T5/20 , G06F13/00
CPC分类号： G06T3/4007 , G06F13/4027 , G06T1/60 , G06T5/20
摘要： A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data. The resampler further includes an interpolation unit, which receives pixel data from the second FIFO memory unit and interpolation fractions from the first FIFO memory unit. The interpolation unit then computes rendered result pixels, assembles the result pixels into memory words and outputs the words to a destination memory address, which is supplied by an address generator in a destination memory subsystem via a third FIFO memory unit.
摘要翻译：提供了一种用于逻辑相邻数据样本的数据处理系统的数据重新采样器。数据重采样器包括用于存储要渲染的样本的存储器子系统，用于生成待渲染样本的插值角地址并且还生成一组插值分数的数字差分分析器（DDA）。重采样器还包括获取单元，其接收所生成的插值角地址，并生成要从存储器子系统取出的样本的四个源地址。重新采样器中包含许多存储单元。第一存储器单元是先进先出的FIFO存储器，用于保持生成的插值分数，并允许DDA和获取单元在存储器读取等待时间期间继续操作。第二存储器单元也是FIFO存储器，用于保存像素数据。再采样器还包括内插单元，其接收来自第二FIFO存储器单元的像素数据和来自第一FIFO存储器单元的插值分数。插值单元然后计算渲染结果像素，将结果像素组装成存储字，并将该字输出到目的地存储器地址，该目的地存储器地址由目的地存储器子系统中的地址发生器经由第三FIFO存储器单元提供。

3. 发明授权

US07062578B2 Flexible processing hardware architecture 有权
标题翻译：灵活的处理硬件架构
公开(公告)号：US07062578B2
公开(公告)日：2006-06-13
申请号：US09977413
申请日：2001-10-15
申请人： David C. Davies , Michael P. Greenberg , Michael J. Wilt , John E. Agapakis
发明人： David C. Davies , Michael P. Greenberg , Michael J. Wilt , John E. Agapakis
IPC分类号： G06F13/00 , H04N7/14
CPC分类号： G06F13/4027 , G06T1/60 , G06T5/20
摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.
摘要翻译：灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接夹层式连接器，并插入个人计算机PCI扩展槽。该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。主系统BIOS将读取类代码，并根据代理卡预留内存。非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的存储空间。

4. 发明授权

US6058434A Apparent network interface for and between embedded and host processors 失效
标题翻译：嵌入式和主机处理器之间的显式网络接口
公开(公告)号：US6058434A
公开(公告)日：2000-05-02
申请号：US26052
申请日：1998-02-19
申请人： Michael J. Wilt , Todd Andrew Ballantyne
发明人： Michael J. Wilt , Todd Andrew Ballantyne
IPC分类号： G06F13/00
CPC分类号： G06F13/00
摘要： An apparent network interface permits one processor such as a processor embedded within a larger processing system (an embedded processor) to communicate to a host processor or other processors and devices on the network to which the embedded processor is attached, using standard network communication mechanisms/protocols such as TCP/IP, NFS, FTP, HTTP, etc. The web server protocol HTTP is particularly useful because it permits the embedded computer to publish a user interface for remote monitoring and remote control using a standard web browser application. The invention provides the host computer with an apparent network interface that appears to be a standard network device, such as an Ethernet interface card. This apparent interface communicates directly with the embedded processor, which appears to be a device on this apparent network. Significant cost savings and performance enhancements are realized by implementing the communication directly over the host computer's peripheral bus rather than using standard network hardware such as Ethernet hardware.
摘要翻译：明显的网络接口允许一个处理器，例如嵌入在较大处理系统（嵌入式处理器）内的处理器，使用标准的网络通信机制/信号来与主机处理器或嵌入式处理器所附网络上的其他处理器和设备通信，协议如TCP / IP，NFS，FTP，HTTP等。Web服务器协议HTTP特别有用，因为它允许嵌入式计算机使用标准Web浏览器应用程序发布用于远程监控和远程控制的用户界面。本发明为主计算机提供看起来像标准网络设备（如以太网接口卡）的明显的网络接口。这个明显的接口直接与嵌入式处理器通信，嵌入式处理器似乎是这个明显的网络上的一个设备。通过直接通过主机计算机的外设总线实现通信，而不是使用诸如以太网硬件的标准网络硬件，实现了显着的成本节约和性能增强。

5. 发明授权

US5926557A Inspection method 失效
标题翻译：检验方法
公开(公告)号：US5926557A
公开(公告)日：1999-07-20
申请号：US824173
申请日：1997-03-26
申请人： Steven Joseph King , Johathan Edmund Ludlow , George Schurr
发明人： Steven Joseph King , Johathan Edmund Ludlow , George Schurr
IPC分类号： G01B11/03 , G01N21/88 , G01N21/956 , G06T1/00 , H05K13/08 , G06K9/00
CPC分类号： H05K13/08 , G01N21/8806 , G01N21/95684
摘要： An inspection system and method uses a ring illumination apparatus to illuminate one or more reflective elements, such as solder balls on an electronic component or other protruding surfaces or objects. The ring illumination apparatus includes a substantially ring-shaped light source that provides a substantially even illumination across the one or more reflective elements. An illumination detection device detects light beams reflecting off of the illuminated reflective elements for forming a reflected image. A method of processing the reflected image includes locating one or more points on each reflected image element representing an illuminated reflective element. The points on the reflected image elements are used to located the pattern of the reflected image elements and/or to fit an outline around each image element corresponding to a known percentage of the true dimensions of each solder ball or other reflective element. The inspection system and method thereby determines various characteristics such as the absence/presence, location, pitch, size and shape of each reflective element.
摘要翻译：检查系统和方法使用环形照明装置来照射一个或多个反射元件，例如电子部件上的焊球或其它突出的表面或物体。环形照明装置包括基本上环形的光源，其在一个或多个反射元件上提供基本均匀的照明。照明检测装置检测用于形成反射图像的照射反射元件反射的光束。处理反射图像的方法包括在表示照明反射元件的每个反射图像元件上定位一个或多个点。反射图像元件上的点用于定位反射图像元素的图案和/或将每个图像元素周围的轮廓与每个焊球或其它反射元件的真实尺寸的已知百分比相对应。检查系统和方法由此确定各种特征，例如每个反射元件的不存在，存在，位置，间距，尺寸和形状。

6. 发明申请

US20060190656A1 Flexible processing hardware architecture 审中-公开
公开(公告)号：US20060190656A1
公开(公告)日：2006-08-24
申请号：US11404193
申请日：2006-04-14
申请人： David Davies , Michael Greenberg , Michael Wilt , John Agapakis
发明人： David Davies , Michael Greenberg , Michael Wilt , John Agapakis
IPC分类号： G06F13/36
CPC分类号： G06T3/4007 , G06F13/4027 , G06T1/60 , G06T5/20
摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.

7. 发明授权

US6041148A System and method for extracting image data 失效
标题翻译：用于提取图像数据的系统和方法
公开(公告)号：US6041148A
公开(公告)日：2000-03-21
申请号：US25937
申请日：1998-02-19
申请人： Michael J. Wilt
发明人： Michael J. Wilt
IPC分类号： G06F13/40 , G06F15/00 , G06T1/20 , G06T1/60 , G06T3/40 , G06T5/20 , G06K9/56
CPC分类号： G06T3/4007 , G06F13/4027 , G06T1/60 , G06T5/20
摘要： A data extraction processor receives data, such as image data, at a high rate of speed and generates processed results, generally at a much lower overall data rate. This sort of processing is particularly useful for machine vision image data, because it can reduce a large image data set to a much smaller data set that is more immediately useful for the currently running application. The data extraction processor may include a segmentation processor, a gradient processor, or other similar types of data extraction processors. The disclosed data extraction processor includes a data flow controller which provides image data to the processors and receives the results from the processors. The data flow controller includes at least one FIFO (first-in, first-out) memory, which allows for the provision of data to the data extraction processor and the receipt of result data therefrom to occur at different rates. Since data extraction algorithms usually generate much less data that they receive, the data flow controller stalls the flow of output data while the analysis proceeds through the data. In some image-dependent situations, however, the analysis may generate more data than it receives. In these situations, the data flow controller stalls the incoming data while the additional results are generated.
摘要翻译：数据提取处理器以高速率接收诸如图像数据的数据，并且通常以低得多的总体数据速率产生处理结果。这种处理对于机器视觉图像数据特别有用，因为它可以将大的图像数据集减少到对当前运行的应用更为直接有用的更小的数据集。数据提取处理器可以包括分割处理器，梯度处理器或其他类似类型的数据提取处理器。所公开的数据提取处理器包括数据流控制器，该数据流控制器向处理器提供图像数据并从处理器接收结果。数据流控制器包括至少一个FIFO（先进先出）存储器，其允许向数据提取处理器提供数据并从其接收结果数据以不同的速率发生。由于数据提取算法通常会生成少得多的数据，所以数据流控制器会在数据分析过程中阻止输出数据的流动。然而，在某些图像相关的情况下，分析可能产生比它接收的更多的数据。在这些情况下，数据流控制器会在输入附加结果生成时停止输入数据。

8. 发明授权

US6118524A Arc illumination apparatus and method 有权
标题翻译：电弧照明装置及方法
公开(公告)号：US6118524A
公开(公告)日：2000-09-12
申请号：US287466
申请日：1999-04-07
申请人： Steven Joseph King , Jonathan Edmund Ludlow
发明人： Steven Joseph King , Jonathan Edmund Ludlow
IPC分类号： G01B11/03 , G01N21/88 , G01N21/956 , H05K13/08 , G01N21/00 , G01B11/14 , H04N7/18 , H04N9/47
CPC分类号： G01N21/8806 , G01N21/95684 , H05K13/08
摘要： An illumination apparatus and method illuminates one or more reflective elements, such as solder balls on an electronic component or other protruding surfaces or objects. The illumination apparatus includes one or more arc shaped or arc shape arranged light sources that provides a substantially even illumination across the one or more reflective elements. An illumination detection device detects light beams reflecting off of the illuminated reflective elements for forming a reflected image. A method of processing the reflected image includes locating one or more points on each reflected image element representing an illuminated reflective element. The points on the reflected image elements are used to located the pattern of the reflected image elements and/or to fit an outline around each image element corresponding to a known percentage of the true dimensions of each solder ball or other reflective element. The inspection system and method thereby determines various characteristics such as the absence/presence, location, pitch, size and shape of each reflective element.
摘要翻译：照明装置和方法照亮一个或多个反射元件，例如电子部件上的焊球或其它突出的表面或物体。照明装置包括一个或多个弧形或弧形布置的光源，其在整个一个或多个反射元件上提供基本均匀的照明。照明检测装置检测用于形成反射图像的照射反射元件反射的光束。处理反射图像的方法包括在表示照明反射元件的每个反射图像元件上定位一个或多个点。反射图像元件上的点用于定位反射图像元素的图案和/或围绕每个图像元素围绕每个焊球或其他反射元件的真实尺寸的已知百分比的轮廓。检查系统和方法由此确定各种特性，例如每个反射元件的不存在，存在，位置，间距，尺寸和形状。

9. 发明授权

US6038352A Two-bit morphology processing apparatus and method 失效
标题翻译：两位形态处理装置及方法
公开(公告)号：US6038352A
公开(公告)日：2000-03-14
申请号：US26053
申请日：1998-02-19
申请人： Michael J. Wilt
发明人： Michael J. Wilt
IPC分类号： G06T1/60 , G06T5/20 , G06T5/30 , G06K9/56
CPC分类号： G06T5/30 , G06T1/60
摘要： The present invention provides a novel system and method that permits a "mask" to be directly incorporated into an image during image processing. This is accomplished by processing binary images or image data which are encoded using two bits rather than the usual one. The second bit is defined to be a "mask enable", which directs a processor to pass the original data through to the output image regardless of the processing result for that pixel. The present invention also provides a means of automatically providing background data to the processor for pixels outside the original image so that the result image is always the same size as the original image. For binary images, the background may be defined to have a value of "0" or "1", and this value is provided to the processing engine in place of all of the pixels which lie outside the original image. For gray-scale images, the minimum or maximum possible value is provided to the processing engine in place of all of the pixels which lie outside of the original image, effectively eliminating these values from consideration when the minimum or maximum of the neighborhood pixels is computed. The determination of whether a pixel is outside of the original image is implemented using the framing signals provided by a data flow controller along with the image data.
摘要翻译：本发明提供一种新颖的系统和方法，其允许在图像处理期间将“掩模”直接结合到图像中。这是通过处理使用两个比特而不是常规编码的二进制图像或图像数据来实现的。第二位被定义为“掩码使能”，其指示处理器将原始数据传递到输出图像，而不管该像素的处理结果如何。本发明还提供了一种自动向处理器提供原始图像外的像素的背景数据的装置，使得结果图像总是与原始图像大小相同。对于二进制图像，背景可以被定义为具有值“0”或“1”，并且该值被提供给处理引擎，而不是位于原始图像之外的所有像素。对于灰度图像，将最小或最大可能值提供给处理引擎，代替位于原始图像之外的所有像素，当计算邻近像素的最小值或最大值时，有效地消除这些值。。使用由数据流控制器提供的成帧信号以及图像数据来确定像素是否在原始图像之外。

10. 发明申请

US20020149895A1 Power control system and method for illumination array 有权
标题翻译：照明阵列功率控制系统及方法
公开(公告)号：US20020149895A1
公开(公告)日：2002-10-17
申请号：US10047949
申请日：2002-01-14
申请人： Acuity Imaging, LLC
发明人： Michael Philip Greenberg
IPC分类号： H02H005/04
CPC分类号： H05B33/089 , H05B33/0851 , H05B33/0887
摘要： A power control system and method controls power supplied from a power source to a resistive load, such as a LED illumination array, to prevent the load from exceeding a high temperature limit. The power control system and method generates a pulse train that represents heating in the load and uses digital logic to model the load temperature and calculate a temperature out value. When the temperature out value increases to reach a high temperature limit value, the power source is disconnected from the load. When the temperature out value decreases to reach a base temperature value, the power source is re-connected to the load.
摘要翻译：电力控制系统和方法控制从电源向诸如LED照明阵列的电阻负载提供的电力，以防止负载超过高温限制。功率控制系统和方法产生表示负载中的加热的脉冲串，并使用数字逻辑来建模负载温度并计算出温度值。当温度上升值达到高温限制值时，电源与负载断开。当温度降低值达到基本温度值时，电源将重新连接到负载。

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