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81. 发明授权

US06954490B2 Fully integrated ethernet transmitter architecture with interpolating filtering 有权
标题翻译：具有内插滤波功能的完全集成的以太网发射机架构
公开(公告)号：US06954490B2
公开(公告)日：2005-10-11
申请号：US10162974
申请日：2002-06-05
申请人： Kevin T. Chan
发明人： Kevin T. Chan
IPC分类号： H04B1/38 , H04B3/00 , H04B3/23 , H04B15/00 , H04J11/00 , H04L5/16 , H04L12/10 , H04L25/00 , H04L25/02 , H04L25/03 , H04L25/08 , H04L25/14 , H04L25/49 , H04L27/00 , H04L27/04
CPC分类号： H04L25/08 , H04B3/23 , H04B3/32 , H04L12/10 , H04L25/0276 , H04L25/0282 , H04L25/0286 , H04L25/03834 , H04L25/14
摘要： A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.
摘要翻译：用于非屏蔽双绞线（UTP）数据通信应用的功率高效和降低的电磁干扰（EMI）发射器。发送数据由N内插并由数字滤波器处理以获得特定通信应用所需的脉冲形状。数字滤波器输出数据通过数/模转换器（DAC）转换为电流模式模拟波形。数字滤波器与DAC二进制解码器集成在诸如具有时间复用输出的ROM的存储器件中。当以这种方式实现时，逻辑实现和存储器替代了常规地以硬件实现的数字滤波电路，DAC解码逻辑电路和重新同步逻辑电路。因此，这些电路的硬件功能被呈现为算术形式并在存储器件中实现。

82. 发明授权

US06870423B2 Output circuit capable of transmitting signal with optimal amplitude and optimal common-mode voltage at receiver circuit 有权
标题翻译：输出电路能够以接收机电路的最佳幅度和最佳共模电压传输信号
公开(公告)号：US06870423B2
公开(公告)日：2005-03-22
申请号：US10405241
申请日：2003-04-03
申请人： Hideki Takauchi , Tomokazu Higuchi
发明人： Hideki Takauchi , Tomokazu Higuchi
IPC分类号： H03K19/0175 , H03K5/003 , H03K5/02 , H03F3/45 , H03K19/094
CPC分类号： H03K5/023 , H03K5/003 , H04L25/0276
摘要： An output circuit has a data control circuit, a variable resistance circuit, a common-mode voltage detection circuit, an adjusting circuit. The data control circuit controls data included in an output signal according to an input signal, the variable resistance circuit is connected in series with the data control circuit between a first power supply line and a second power supply line. Further, the common-mode voltage detection circuit detects a common-mode voltage of the output signal, and the adjusting circuit adjusts a resistance of the variable resistance circuit according to an output of the common-mode voltage detection circuit. The common-mode voltage of the output signal is adjusted to equal an optional voltage, and an amplitude of the output signal is adjustable.
摘要翻译：输出电路具有数据控制电路，可变电阻电路，共模电压检测电路，调整电路。数据控制电路根据输入信号控制包含在输出信号中的数据，可变电阻电路与第一电源线和第二电源线之间的数据控制电路串联连接。此外，共模电压检测电路检测输出信号的共模电压，调节电路根据共模电压检测电路的输出调节可变电阻电路的电阻。输出信号的共模电压被调整为等于可选电压，输出信号的幅度可调。

83. 发明授权

US06870390B1 Tx line driver with common mode idle state and selectable slew rates 有权
标题翻译： Tx线驱动器，具有共模闲置状态和可选择的转换速率
公开(公告)号：US06870390B1
公开(公告)日：2005-03-22
申请号：US10660448
申请日：2003-09-11
申请人： Eric D. Groen , Charles W. Boecker , William C. Black
发明人： Eric D. Groen , Charles W. Boecker , William C. Black
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003 , H03K19/0185 , H04L25/02 , H04L27/10
CPC分类号： H04L25/028 , H03K19/018514 , H03K19/018585 , H04L25/0276 , H04L25/0278 , H04L25/0292 , H04L27/10
摘要： A transmit line driver with selectable slew rates and a common mode idle state comprises a capacitor array of selectable capacitors coupled between a line driver and a pre-driver wherein a slew rate may be selected by the selectable capacitors. A common mode idle state is provided by coupling a selectable switch (MOSFET in the described embodiment) to a mirror device that provides a bias current to the pre-driver wherein, when the bias current is removed by the switch, the pre-driver produces an output signal that is equal to the supply voltage for the circuit. Accordingly, a differential pair of the line driver are both biased on and provide a common mode idle state. The common mode idle state is equal to one half of an output signal magnitude for a logic one.
摘要翻译：具有可选择的转换速率和共模空闲状态的发送线路驱动器包括耦合在线路驱动器和预驱动器之间的可选择电容器的电容器阵列，其中可选择的电容器可以选择转换速率。通过将可选开关（所述实施例中的MOSFET）耦合到向预驱动器提供偏置电流的反射镜装置来提供共模空闲状态，其中当偏置电流被开关去除时，前驱动器产生输出信号等于电路的电源电压。因此，线路驱动器的差分对都被偏置并提供共模空闲状态。共模空闲状态等于逻辑1的输出信号幅度的一半。

84. 发明授权

US06788101B1 Programmable interface circuit for differential and single-ended signals 有权
公开(公告)号：US06788101B1
公开(公告)日：2004-09-07
申请号：US10366956
申请日：2003-02-13
申请人： Arifur Rahman
发明人： Arifur Rahman
IPC分类号： H03K19003
CPC分类号： H04L25/0276 , H03K19/017581 , H04L25/028 , H04L25/0292
摘要： A programmable interface circuit is disclosed, in accordance with one embodiment, which supports differential and single-ended signaling. For example, an input buffer within the programmable interface circuit is configurable to receive differential signals or single-ended signals. A multiplexer provides the appropriate reference signal to the input buffer, when configured to receive single-ended signals, by selecting the reference signal from a plurality of reference buses. The multiplexer, along with a capacitor, may also provide lowpass filtering of the reference signal. Furthermore, an output buffer may be configurable utilizing techniques similar to that described for the input buffer.

85. 发明授权

US06762625B1 Programmable differential current mode line driver with multiple classes of circuit operation 有权
标题翻译：可编程差分电流模式线路驱动器，具有多类电路操作
公开(公告)号：US06762625B1
公开(公告)日：2004-07-13
申请号：US10304108
申请日：2002-11-25
申请人： Varadarajan Devnath
发明人： Varadarajan Devnath
IPC分类号： H03K1920
CPC分类号： H04L25/0272 , H04L25/0276 , H04L25/0278 , H04L25/0282
摘要： A programmable differential current mode line driver with multiple classes of circuit operation that can be digitally programmed to operate in a low distortion, low noise class A mode or a low power class B mode, with multiple signal levels available in each mode of operation.
摘要翻译：具有多种电路操作的可编程差分电流模式线路驱动器，可以进行数字编程，以在低失真，低噪声等级A模式或低功率B类模式下工作，每种工作模式都有多个信号电平。

86. 发明申请

US20040131123A1 Balanced transmission apparatus 审中-公开
标题翻译：平衡传动装置
公开(公告)号：US20040131123A1
公开(公告)日：2004-07-08
申请号：US10685411
申请日：2003-10-16
发明人： Masahiro Maki , Yuji Igata , Junji Kondou , Toshiyuki Wakisaka , Takao Gondo
IPC分类号： H04B003/00 , H04L025/00
CPC分类号： H04L25/0276 , H04B3/54 , H04B2203/5425 , H04B2203/5458 , H04B2203/547 , H04B2203/5487 , H04L25/028 , H04L25/0292 , H04L25/10
摘要： In a transmitter, either the voltage or the current, or both applied to each of a pair of conductors is monitored. In a receiver either the voltage or the current, or both outputted from each conductor are monitored, thereafter the status will be outputted. Using the outputted status, either the voltage or the current, or both applied to the conductors in a transmitter will be controlled. This makes it possible to improve the degree of balance in the receiver while keeping the balance in the transmitter, which results in reducing EMC problems both in the transmitter and the receiver.
摘要翻译：在发射机中，监视施加到一对导体中的每一个的电压或电流，或者两者。在接收机中，监视从每个导体输出的电压或电流，或者两者都输出，此后状态将被输出。使用输出状态，电压或电流，或两者都被施加到发射机中的导体。这使得可以在保持发射机中的平衡的同时提高接收机的平衡度，这导致在发射机和接收机中都减少EMC问题。

87. 发明授权

US06760381B2 High-voltage differential driver using stacked low-breakdown transistors and nested-miller compensation 失效
标题翻译：高压差分驱动器采用堆叠低击穿晶体管和嵌套式铣刀补偿
公开(公告)号：US06760381B2
公开(公告)日：2004-07-06
申请号：US09681102
申请日：2001-01-05
申请人： Crist Y. Lu
发明人： Crist Y. Lu
IPC分类号： H04B300
CPC分类号： H04L25/028 , H03F3/45192 , H04L25/0276
摘要： An amplifier drives a Digital-Subscriber Line (DSL) using a 12-volt power supply. Ordinary low-voltage transistors for 5-volt systems are stacked together to reduce the average voltage across each transistor to below a breakdown voltage. The output stage uses p-channel and n-channel driver transistors that are coupled to differential outputs through cascode transistors. A common-mode voltage is fed back to a second stage to adjust signals for deviations in the common-mode output bias. A first stage buffers a pair of differential inputs to the second stage. The second stage uses level shifting to generate four signals to the output stage driver transistors. A pair of high-voltage signals drives the p-channel drivers while a pair of low-voltage signals drives the n-channel driver transistors. Nested miller compensation stabilizes the amplifier using capacitors between the final outputs and the four signals from the second stage and the differential signals from the first stage.
摘要翻译：放大器使用12伏电源驱动数字用户线（DSL）。用于5伏系统的普通低压晶体管堆叠在一起，以将每个晶体管的平均电压降低到击穿电压以下。输出级使用通过共源共栅晶体管耦合到差分输出的p沟道和n沟道驱动晶体管。将共模电压反馈到第二级，以调整共模输出偏压中的偏差信号。第一级将一对差分输入缓冲到第二级。第二级使用电平移位来产生四个信号到输出级驱动晶体管。一对高电压信号驱动p沟道驱动器，而一对低电压信号驱动n沟道驱动晶体管。嵌套磨机补偿使放大器在最终输出和来自第二级的四个信号和来自第一级的差分信号之间使用电容器稳定。

88. 发明申请

US20040105504A1 Adaptively configurable class-A/class-B transmit DAC for transceiver emission and power consumption control 失效
公开(公告)号：US20040105504A1
公开(公告)日：2004-06-03
申请号：US10717127
申请日：2003-11-19
发明人： Kevin T. Chan
IPC分类号： H04L027/04 , H04B003/00
CPC分类号： H04L25/08 , H04B3/23 , H04B3/32 , H04L12/10 , H04L25/0276 , H04L25/0282 , H04L25/0286 , H04L25/03834 , H04L25/14
摘要： A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode. For a multi-transmitter system, timing circuitry staggers the time base of each transmitter to reduce the aggregate EMI emissions of the multi-transmitter system.

89. 发明授权

US06731135B2 Low voltage differential signaling circuit with mid-point bias 有权
标题翻译：低电压差分信号电路具有中点偏置
公开(公告)号：US06731135B2
公开(公告)日：2004-05-04
申请号：US09991107
申请日：2001-11-16
申请人： Michael J. Brunolli
发明人： Michael J. Brunolli
IPC分类号： H03K190175
CPC分类号： H04L25/0276 , H03F3/45179 , H03F2203/45008 , H04L25/0278 , H04L25/028
摘要： A low voltage differential signaling circuit employs a mid-point biasing scheme that maintains a desired common mode voltage across all logic states signaled by the circuit. In one driver implementation, separate conduction paths are used to signal respective logic states on a pair of differential signal lines. A common pair of resistors are provided in the conduction path between the two signal lines. The midpoint between the pair of resistors is tied to the desired common mode voltage. A midpoint bias circuit is coupled to a variable resistance in the conduction path so as to maintain the desired common mode voltage by virtue of a voltage division so as to minimize the amount of non-conduction path current at the mid point node. In one example, a replica circuit further provides an anticipated midpoint voltage to the midpoint bias circuit for comparison to the desired midpoint voltage. The midpoint bias circuit adjusts the variable resistance in accordance with the comparison.
摘要翻译：低电压差分信号电路采用中点偏置方案，其保持由电路发出信号的所有逻辑状态所需的共模电压。在一个驱动器实现中，使用单独的导通路径来信号对一对差分信号线上的逻辑状态。在两个信号线之间的传导路径中设置一对共同的电阻器。该对电阻之间的中点连接到所需的共模电压。中点偏置电路耦合到导通路径中的可变电阻，以便通过分压来保持所需的共模电压，以便最小化中点节点处的非导通路径电流的量。在一个示例中，复制电路进一步向中点偏置电路提供预期的中点电压，以与期望的中点电压进行比较。中点偏置电路根据比较调整可变电阻。

90. 发明授权

US06714588B1 Method and apparatus for interference cancellation in a high speed modem 失效
标题翻译：高速调制解调器干扰消除的方法和装置
公开(公告)号：US06714588B1
公开(公告)日：2004-03-30
申请号：US09429495
申请日：1999-10-29
申请人： Robert McLaren Thomas , Carl William Anderson , Michael Henry Dziawa
发明人： Robert McLaren Thomas , Carl William Anderson , Michael Henry Dziawa
IPC分类号： H04L516
CPC分类号： H04L25/08 , H04L12/2854 , H04L25/0276 , H04L27/2647
摘要： A method and apparatus for interference cancellation in a high-speed modem that includes a first coupler for receiving a differential signal including a received data signal, a second coupler for deriving a common mode signal for the transmitted signal, and a phase-shift circuit coupled to the second coupler for deriving orthogonal signals from the common mode signal. First and second multipliers mix the orthogonal signals with the received signal. First, second, and third integrators integrate the mixed orthogonal signals and the common mode signal to produce orthogonal signal level measurements ITONE and QTONE and a common mode signal level measurement CMTONE, respectively. A controller derives orthogonal correction signals from measurements by dividing ITONE and QTONE respectively by CMTONE and multiplying by an appropriate constant. This output is then used to increment or decrement the signals to the respective digital to analog converters, DACI and DACQ. Multipliers combine these orthogonal correction signals to the orthogonal signals. An adder the combines the corrected orthogonal signals with the received signal for deriving the received data signal by cancelling interference therein.
摘要翻译：一种用于高速调制解调器中的干扰消除的方法和装置，包括：第一耦合器，用于接收包括接收到的数据信号的差分信号;第二耦合器，用于导出所发送的信号的共模信号;以及相移电路，到第二耦合器，用于从共模信号导出正交信号。第一和第二乘法器将正交信号与接收信号混合。第一，第二和第三积分器将混合正交信号和共模信号进行积分，分别产生正交信号电平测量值ITONE和QTONE以及共模信号电平测量CMTONE。控制器通过分割ITONE和QTONE分别通过CMTONE并乘以适当的常数从测量中得到正交校正信号。然后，该输出用于将信号递增或递减到相应的数模转换器DACI和DACQ。乘法器将这些正交校正信号组合成正交信号。加法器将经校正的正交信号与接收信号组合，以通过消除接收的数据信号来消除接收的数据信号。

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