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81. 发明授权

US06670858B2 High speed voltage-controlled ring oscillator 有权
公开(公告)号：US06670858B2
公开(公告)日：2003-12-30
申请号：US10004364
申请日：2001-11-01
申请人： Benjamim Tang
发明人： Benjamim Tang
IPC分类号： H03B2700
CPC分类号： H03L7/10 , H03K3/0231 , H03K3/03 , H03K3/0322 , H03L7/0998 , H03L7/189
摘要： A high speed ring voltage-controlled oscillator (VCO) system is provided. The ring VCO system includes a plurality of interpolation stages coupled in a “look-ahead” configuration. Each interpolation stage receives two signal inputs and outputs a single differential voltage representative of a time delay interpolation between the two input signals. In accordance with the invention, each interpolation stage receives a first signal input from the immediately previous stage and a second signal input from the output of a different stage. In this manner, the delay stages in the ring VCO can generate a variable delay by interpolating between inputs with small relative delays without adding additional delay to the total loop delay.

82. 发明授权

US06636576B1 Method for reducing the settling time in PLL circuits 有权
标题翻译：降低PLL电路稳定时间的方法
公开(公告)号：US06636576B1
公开(公告)日：2003-10-21
申请号：US09413713
申请日：1999-10-05
申请人： Pietro Filoramo , Gaetano Cosentino
发明人： Pietro Filoramo , Gaetano Cosentino
IPC分类号： H03L7093
CPC分类号： H03L7/189
摘要： A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, the PLL circuits including a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage (VC) for controlling a voltage-controlled oscillator provided by means of a varactor, the method including determining the dependency of the control voltage (VC) of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current (IDAC) of the digital-analog converter such that the voltage (VDAC) obtained from the output current of the digital-analog converter, added to an output voltage (Vf) of said filter keeps the filter voltage (Vf) constant in order to reduce the settling time of the PLL circuit as a selected channel varies.
摘要翻译：一种用于减少PLL电路中的建立时间的方法，特别是用于RF收发器中的PLL电路包括相位比较器，滤波器，数模转换器和加法器，其适于在输出端产生电压（VC）用于控制通过变容二极管提供的压控振荡器，所述方法包括确定压控振荡器的控制电压（VC）对发射机所选频道的频率的依赖性; 以及产生描述所述数模转换器的输出电流（IDAC）的变化的定律，使得从所述数模转换器的输出电流获得的电压（VDAC）加到所述滤波器的输出电压（Vf）上保持滤波电压（Vf）恒定，以便随着所选通道的变化而减小PLL电路的稳定时间。

83. 发明授权

US06614315B2 Tuning circuit for a YIG oscillator 有权
公开(公告)号：US06614315B2
公开(公告)日：2003-09-02
申请号：US09878395
申请日：2001-06-12
申请人： Alexander Roth
发明人： Alexander Roth
IPC分类号： H03L700
CPC分类号： H03L7/099 , H03L7/18 , H03L7/189 , H03L2207/06
摘要： In the case of a tuning circuit for a YIG oscillator, wherein the output frequency of the YIG oscillator which is reduced by a frequency divider or mixer is compared in a phase detector with a lower reference frequency and via a loop filter the output voltage of the phase detector feeds the air-cored coil of the YIG oscillator serving for fine tuning, the main coil of the YIG oscillator is also fed by the output voltage of the phase detector.

84. 发明申请

US20030118141A1 Method for measuring the response of a voltage controlled oscillator 失效
标题翻译：测量压控振荡器响应的方法
公开(公告)号：US20030118141A1
公开(公告)日：2003-06-26
申请号：US10024416
申请日：2001-12-21
申请人： Xerox Corporation
发明人： Michael B. Neary
IPC分类号： H03D003/24
CPC分类号： H03L7/189 , H03L7/199 , H04N1/053 , H04N1/1135 , H04N1/12 , H04N2201/02439 , H04N2201/02443 , H04N2201/0471 , H04N2201/04732 , H04N2201/04744 , H04N2201/04758 , H04N2201/04772 , H04N2201/04794 , H04N2201/04798
摘要： A method for calibrating a VCO within a phase locked loop circuit is disclosed. First, a DAC output voltage is set to its minimum, and a counter M is adjusted until a comparator is its threshold voltage. Next, the DAC is set to another voltage, and counter M is again adjusted to the comparator threshold. This process is repeated for as many steps as desired. When the phase locked loop circuit requests an instantaneous frequency, an interpolation of the requested frequency against the curve created by the above-described method gives the value required by the DAC.
摘要翻译：公开了一种在锁相环电路内校准VCO的方法。首先，将DAC输出电压设置为最小值，并且调整计数器M直到比较器为其阈值电压。接下来，将DAC设置为另一电压，并且将计数器M再次调整为比较器阈值。根据需要重复这个步骤。当锁相环电路请求瞬时频率时，根据上述方法产生的曲线对所请求频率的插值给出DAC需要的值。

85. 发明申请

US20030099320A1 Methods and devices for improving the switching times of PLLs 失效
标题翻译：提高PLL切换时间的方法和设备
公开(公告)号：US20030099320A1
公开(公告)日：2003-05-29
申请号：US09994847
申请日：2001-11-28
发明人： Roman Z. Arkiszewski
IPC分类号： H03D003/24
CPC分类号： H03L7/0891 , H03L7/189
摘要： The switching time of a phase-locked loop circuit is improved by switching a direct frequency control section, into and out of, the circuit.
摘要翻译：通过将直接频率控制部分切换到电路中并使电路切换，来改善锁相环电路的切换时间。

86. 发明授权

US06441690B1 Phase-locked loop frequency synthesizer 失效
标题翻译：锁相环频率合成器
公开(公告)号：US06441690B1
公开(公告)日：2002-08-27
申请号：US09645360
申请日：2000-08-25
申请人： Patrick Savelli , Christian Massy
发明人： Patrick Savelli , Christian Massy
IPC分类号： H03C309
CPC分类号： H03C3/0983 , H03C3/0941 , H03C3/095 , H03C3/0975 , H03L7/189
摘要： A phase-locked loop frequency synthesizer includes circuitry which determines the real gain of a voltage-controlled oscillator from at least one measurement parameter and delivers a signal representative of the real gain of the voltage-controlled oscillator.
摘要翻译：锁相环频率合成器包括从至少一个测量参数确定压控振荡器的实际增益的电路，并传送代表压控振荡器的实际增益的信号。

87. 发明申请

US20020079973A1 Automatic bias adjustment circuit for use in PLL circuit 有权
标题翻译：用于PLL电路的自动偏置调整电路
公开(公告)号：US20020079973A1
公开(公告)日：2002-06-27
申请号：US09988618
申请日：2001-11-20
申请人： FUJITSU LIMITED
发明人： Hirohito Higashi , Hideki Ishida
IPC分类号： H03L007/00
CPC分类号： H03L7/0805 , H03L1/022 , H03L7/0893 , H03L7/10 , H03L7/189
摘要： A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is reverse to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.
摘要翻译：另外提供给PLL电路中的电流控制电路13的偏置电流IB是由偏置调整电路（18,19,20,21和22）产生的偏置电流IB1和IB2的和，并产生偏置电流电路（23和24）。偏置调整电路响应于调节开始信号ADJ调节偏置电流IB1，使得控制电压VC收敛到参考电压VREF，并且在已经达到收敛时停止调整。参考电压VREF被确定为在PLL电路中的变量VC的范围内的几乎中点处的值。偏置电流产生电路具有产生偏置电压VT的电路23和将VT转换成电流IB2的电路24，其中偏置电压VT的温度特性与控制电压VC的温度特性相反，的振荡信号OCLK是固定的。

88. 发明授权

US06411237B1 Nonlinear digital-to-analog converters 失效
标题翻译：非线性数模转换器
公开(公告)号：US06411237B1
公开(公告)日：2002-06-25
申请号：US09540352
申请日：2000-03-31
申请人： Lloyd L. Lautzenhiser
发明人： Lloyd L. Lautzenhiser
IPC分类号： H03M166
CPC分类号： H03L7/189
摘要： Digital-to-analog converters (282, 292, 310, 340, or 370) produce intentionally nonlinear outputs. When outputs of a plurality of lower bits are replaced by a next higher bit, a downward step (281 or 330) is produced in an output voltage (276, 332, or 336). Each of the downward steps (281 or 330) results in production of substantially equal output voltages in response to two different digital numbers being inputted. The digital-to-analog converters (282, 292, 310, 340, or 370) of the present invention are useful in frequency-hopping oscillators (72, 136, 170, or 190), in phase-locked oscillators (10, 74, 152, 172, and 196), and in other electronic systems that include a learning path (222, 224, or 226) with a digital-to-analog converter.
摘要翻译：数模转换器（282,292,310,340或370）产生有意非线性的输出。当多个低位的输出被下一较高位代替时，在输出电压（276,332或336）中产生向下的步（281或330）。每个向下的步骤（281或330）导致响应于输入的两个不同数字数字产生基本上相等的输出电压。在锁相振荡器（10,74）中，本发明的数模转换器（282,292,310,340或370）可用于跳频振荡器（72,136,170或190），152,172和196）以及在包括数字 - 模拟转换器的学习路径（222,224或226）的其他电子系统中。

89. 发明授权

US06380809B1 Method and apparatus for tuning oscillator to a selected frequency 失效
标题翻译：将振荡器调谐到选定频率的方法和装置
公开(公告)号：US06380809B1
公开(公告)日：2002-04-30
申请号：US09507392
申请日：2000-02-18
申请人： William O. Camp, Jr.
发明人： William O. Camp, Jr.
IPC分类号： H03L700
CPC分类号： H03L7/146 , H03L7/189
摘要： The present invention discloses an apparatus and method for tuning an oscillator to a selected frequency during power measurements of a neighbor list. In response to a received request for the oscillator to tune to a selected frequency, a controller associated with a switch determines whether the request comprises a first request for the oscillator to tune to the selected frequency. If so, the switch is placed in a first position, and the oscillator is provided a voltage control signal from a phase locked loop. The voltage control signal applied to the input of the oscillator is also saved at a location associated with the selected frequency. If the controller determines that the request does not comprise a first request for the selected frequency, a previously saved voltage control signal associated with the selected frequency is applied to the input of the oscillator by placing the switch in a second position. In either case, the oscillator is tuned to the selected frequency responsive to the applied voltage control signal.
摘要翻译：本发明公开了一种用于在邻近列表的功率测量期间将振荡器调谐到选定频率的装置和方法。响应于接收到的振荡器调谐到所选频率的请求，与开关相关联的控制器确定该请求是否包括用于振荡器调谐到所选频率的第一请求。如果是这样，则将开关置于第一位置，并且从振荡器提供来自锁相环的电压控制信号。施加到振荡器的输入端的电压控制信号也保存在与所选频率相关联的位置处。如果控制器确定请求不包括对所选频率的第一请求，则将与所选频率相关联的先前保存的电压控制信号通过将开关置于第二位置而被施加到振荡器的输入。在任一种情况下，响应所施加的电压控制信号将振荡器调谐到所选择的频率。

90. 发明授权

US6091943A Combining oscillator with a phase-indexed control circuit for a radio receiver 失效
标题翻译：将振荡器与无线电接收机的相位索引控制电路相结合
公开(公告)号：US6091943A
公开(公告)日：2000-07-18
申请号：US91372
申请日：1998-06-17
申请人： Detlev Nyenhuis
发明人： Detlev Nyenhuis
IPC分类号： H03L7/093 , H03J1/00 , H03L7/107 , H03L7/189 , H04B1/06
CPC分类号： H03J1/0066 , H03L7/189
摘要： A mixer oscillator with a phase-locked loop control loop for a radio receiver is described in which a digital loop filter in the control loop includes which an integrator for digital output signals of a phase discriminator which is preprogrammed frequency jumps. The digital loop filter includes two switchable integrators for optional alternate switching of alternate test frequencies.
摘要翻译： PCT No.PCT / DK96 / 00517 Sec。 371日期1998年6月17日第 102（e）1998年6月17日PCT 1996年12月9日PCT PCT。第WO97 / 23957号公报日期1997年7月3日描述了一种用于无线电接收机的具有锁相环控制回路的混频器振荡器，其中控制回路中的数字环路滤波器包括用于预编程频率跳变的相位鉴别器的数字输出信号的积分器。数字环路滤波器包括两个可切换的积分器，用于替代测试频率的可选替代切换。

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