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81. 发明授权

US08980731B2 Methods of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US08980731B2
公开(公告)日：2015-03-17
申请号：US13724632
申请日：2012-12-21
申请人： Samsung Electronics Co., Ltd.
发明人： Jung Ho Kim , Sunghae Lee , Hanvit Yang , Dongwoo Kim , Chaeho Kim , Daehyun Jang , Ju-Eun Kim , Yong-Hoon Son , Sangryol Yang , Myoungbum Lee , Kihyun Hwang
IPC分类号： H01L21/04 , H01L21/82 , H01L21/336 , H01L21/3205 , H01L29/76 , H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L21/04 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.
摘要翻译：提供了形成半导体器件的方法。所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。所述方法还可以包括在开口中形成第一半导体图案。所述方法还可以包括在第一半导体图案上形成绝缘图案。所述方法还可以包括在绝缘图案上形成第二半导体图案。所述方法还可以包括在第一半导体图案中提供掺杂剂。此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

82. 发明申请

US20150072504A1 HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS 有权
标题翻译：用于低失真电路应用的高线性SOI波形
公开(公告)号：US20150072504A1
公开(公告)日：2015-03-12
申请号：US14546058
申请日：2014-11-18
申请人： International Business Machines Corporation
发明人： Alan B. Botula , Jeffrey E. Hanrahan , Mark D. Jaffe , Alvin J. Joseph , Dale W. Martin , Gerd Pfeiffer , James A. Slinkman
IPC分类号： H01L21/762 , H01L21/324 , H01L21/265
CPC分类号： H01L21/76251 , H01L21/04 , H01L21/265 , H01L21/26506 , H01L21/324
摘要： According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
摘要翻译：根据本文的方法，在第一材料被植入之后，衬底的第一侧被注入第一材料，以将衬底的第一侧的结晶结构从第一结晶状态改变到第二结晶状态。在植入第一种材料之后，第二种材料沉积在基底的第一面上。绝缘体层的第一面在衬底的第一侧上与第二材料接合。在绝缘体层与第二材料结合之后，在绝缘体层的与绝缘体层的第一侧相对的第二侧上形成集成电路器件。集成电路器件进行热退火。第一种材料在退火过程中保持衬底的第一面的第二结晶状态。

83. 发明授权

US08883609B2 Method for manufacturing a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US08883609B2
公开(公告)日：2014-11-11
申请号：US14086144
申请日：2013-11-21
申请人： Infineon Technologies Austria AG
发明人： Mathias Plappert , Hans-Joachim Schulze
IPC分类号： H01L21/76 , H01L21/02 , H01L21/265 , H01L21/28 , H01L21/324 , H01L29/43 , H01L29/04 , H01L21/04
CPC分类号： H01L21/02595 , H01L21/02532 , H01L21/02592 , H01L21/02598 , H01L21/02609 , H01L21/02667 , H01L21/04 , H01L21/187 , H01L21/265 , H01L21/28 , H01L21/324 , H01L29/04 , H01L29/43 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
摘要翻译：根据实施例，一种制造半导体结构的方法包括提供在参考方向上具有第一晶格常数的第一单晶半导体部分，并形成在参考方向上具有第二晶格常数的第二单晶半导体部分，其与第一晶格常数，在第一单晶半导体部分上。

84. 发明申请

US20140209973A1 Reverse Blocking Semiconductor Device, Semiconductor Device with Local Emitter Efficiency Modification and Method of Manufacturing a Reverse Blocking Semiconductor Device 有权
标题翻译：反向阻塞半导体器件，具有局部发射极效率改进的半导体器件和制造反向阻塞半导体器件的方法
公开(公告)号：US20140209973A1
公开(公告)日：2014-07-31
申请号：US13754943
申请日：2013-01-31
申请人： INFINEON TECHNOLOGIES AG
发明人： Johannes Georg Laven , Roman Baburske , Christian Jaeger , Hans-Joachim Schulze
IPC分类号： H01L29/739 , H01L21/04
CPC分类号： H01L27/0664 , H01L21/04 , H01L29/0634 , H01L29/0834 , H01L29/66143 , H01L29/6634 , H01L29/66348 , H01L29/7393 , H01L29/7397
摘要： A reverse blocking semiconductor device includes a base region of a first conductivity type and a body region of a second, complementary conductivity type, wherein the base and body regions form a pn junction. Between the base region and a collector electrode an emitter layer is arranged that includes emitter zones of the second conductivity type and at least one channel of the first conductivity type. The channels extend through the emitter layer between the base region and the collector electrode and reduce the leakage current in a forward blocking state.
摘要翻译：反向阻挡半导体器件包括第一导电类型的基极区域和第二互补导电类型的体区域，其中基极区域和主体区域形成pn结。在基极区域和集电极电极之间布置发射极层，其包括第二导电类型的发射区和至少一个第一导电类型的沟道。通道延伸穿过基极区域和集电极之间的发射极层，并且在正向阻挡状态下减小漏电流。

85. 发明申请

US20140209970A1 Semiconductor Device Including an Edge Area and Method of Manufacturing a Semiconductor Device 有权
标题翻译：包括边缘区域的半导体器件和制造半导体器件的方法
公开(公告)号：US20140209970A1
公开(公告)日：2014-07-31
申请号：US13754957
申请日：2013-01-31
申请人： INFINEON TECHNOLOGIES AG
发明人： Hans-Joachim Schulze , Anton Mauder , Franz Hirler
IPC分类号： H01L29/36 , H01L21/04
CPC分类号： H01L29/36 , H01L21/04 , H01L29/0615 , H01L29/0623 , H01L29/0634 , H01L29/0834 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/42368 , H01L29/66128 , H01L29/66136 , H01L29/66348 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/8611
摘要： A semiconductor portion of a semiconductor device includes a semiconductor layer with a drift zone of a first conductivity type and at least one impurity zone of a second, opposite conductivity type. The impurity zone adjoins a first surface of the semiconductor portion in an element area. A connection layer directly adjoins the semiconductor layer opposite to the first surface. At a distance to the first surface an overcompensation zone is formed in an edge area that surrounds the element area. The overcompensation zone and the connection layer have opposite conductivity types. In a direction vertical to the first surface, a portion of the drift zone is arranged between the first surface and the overcompensation zone. In case of locally high current densities, the overcompensation zone injects charge carriers into the semiconductor layer that locally counter a further increase of electric field strength and reduce the risk of avalanche breakdown.
摘要翻译：半导体器件的半导体部分包括具有第一导电类型的漂移区和具有第二相反导电类型的至少一个杂质区的半导体层。杂质区在元件区域中邻接半导体部分的第一表面。连接层直接邻接与第一表面相对的半导体层。在距离第一表面的距离处，在围绕元件区域的边缘区域中形成过度补偿区域。过补偿区和连接层具有相反的导电类型。在垂直于第一表面的方向上，漂移区的一部分布置在第一表面和过补偿区之间。在局部高电流密度的情况下，过补偿区将电荷载流子注入到半导体层中，其局部地抵消电场强度的进一步增加并降低雪崩击穿的风险。

86. 发明申请

US20140131837A1 GAN VERTICAL BIPOLAR TRANSISTOR 有权
标题翻译： GAN垂直双极晶体管
公开(公告)号：US20140131837A1
公开(公告)日：2014-05-15
申请号：US13675916
申请日：2012-11-13
申请人： AVOGY, INC.
发明人： Hui Nie , Andrew Edwards , Isik Kizilyalli , Dave Bour
IPC分类号： H01L29/73 , H01L21/04
CPC分类号： H01L21/04 , H01L29/0615 , H01L29/2003 , H01L29/42304 , H01L29/66318 , H01L29/732 , H01L29/7371
摘要： An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.
摘要翻译：半导体器件的实施例包括第一导电类型的III族氮化物基底结构和具有第一表面和第二表面的第二导电类型的III族氮化物发射极结构。第二表面基本上与第一表面相对。 III族氮化物发射极结构的第一表面耦合到III族氮化物基底结构的表面。半导体还包括耦合到III族氮化物发射极结构的第二表面的第一电介质层和耦合到III族氮化物发射极结构的侧壁和III族氮化物基底结构的表面的间隔物。该半导体还包括具有连接到间隔物，III族氮化物基底结构的表面和第一介电层的III族氮化物材料的基底接触结构，使得第一介电层和间隔物设置在基底触点结构和III族氮化物发射极结构。

87. 发明申请

US20140131777A1 INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SALICIDE CONTACTS ON NON-PLANAR SOURCE/DRAIN REGIONS 审中-公开
标题翻译：集成电路与非平面电源/漏电区域制造与广泛接触的集成电路的方法
公开(公告)号：US20140131777A1
公开(公告)日：2014-05-15
申请号：US13677651
申请日：2012-11-15
申请人： GLOBALFOUNDRIES, INC.
发明人： Hoong Shing Wong , Min-hwa Chi
IPC分类号： H01L29/78 , H01L21/04
CPC分类号： H01L21/04 , H01L29/665 , H01L29/66795
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a fin over a semiconductor substrate. The method further includes selectively epitaxially growing a silicon-containing material on the fin and providing the fin with a diamond-shaped cross-section and with an upper portion and a lower portion. The lower portion of the fin is covered with a masking layer. Further, a salicide layer is formed on the upper portion of the fin, and the masking layer prevents formation of the salicide layer on the lower portion of the fin.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成翅片。该方法还包括在翅片上选择性地外延生长含硅材料，并为翅片提供菱形横截面以及上部和下部。翅片的下部被掩蔽层覆盖。此外，在翅片的上部形成有自对准硅层，掩模层防止在翅片的下部形成自对准硅化物层。

88. 发明申请

US20140131775A1 VERTICAL GaN JFET WITH LOW GATE-DRAIN CAPACITANCE AND HIGH GATE-SOURCE CAPACITANCE 有权
标题翻译：具有低栅极电容和高栅极电容的垂直GaN JFET
公开(公告)号：US20140131775A1
公开(公告)日：2014-05-15
申请号：US13675694
申请日：2012-11-13
申请人： AVOGY, INC.
发明人： Donald R. Disney
IPC分类号： H01L27/085 , H01L21/04
CPC分类号： H01L29/66909 , H01L21/04 , H01L29/66462 , H01L29/66924 , H01L29/8083
摘要： An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type.
摘要翻译：垂直功率器件的实施例包括III族氮化物衬底，耦合到III族氮化物衬底并包括第一导电类型的III族氮化物材料的漂移区域和耦合到漂移区域的沟道区域，并且包括III - 第一导电类型的氮化物材料。垂直功率器件还包括耦合到沟道区并且包括第一导电类型的III族氮化物材料的源极区域和耦合到沟道区域的栅极区域。栅极区域包括第二导电类型的III族氮化物材料。垂直功率器件还包括耦合到漂移区并与源极区域电连接的源极耦合区域。源极耦合区域包括第二导电类型的III族氮化物材料。

89. 发明申请

US20140120648A1 COMPOSITION FOR FORMING N-TYPE DIFFUSION LAYER, METHOD OF FORMING N-TYPE DIFFUSION LAYER, AND METHOD OF PRODUCING PHOTOVOLTAIC CELL 有权
标题翻译：用于形成N型扩散层的组合物，形成N型扩散层的方法和生产光伏电池的方法
公开(公告)号：US20140120648A1
公开(公告)日：2014-05-01
申请号：US14076225
申请日：2013-11-10
申请人： Yoichi MACHII , Masato YOSHIDA , Takeshi NOJIRI , Kaoru OKANIWA , Mitsunori IWAMURO , Shuichiro ADACHI , Tetsuya SATO , Keiko KIZAWA
发明人： Yoichi MACHII , Masato YOSHIDA , Takeshi NOJIRI , Kaoru OKANIWA , Mitsunori IWAMURO , Shuichiro ADACHI , Tetsuya SATO , Keiko KIZAWA
IPC分类号： H01L31/18 , H01L21/22
CPC分类号： H01L31/0288 , C03C3/097 , C03C8/18 , H01L21/04 , H01L21/22 , H01L21/2225 , H01L21/2255 , H01L31/022425 , H01L31/0236 , H01L31/068 , H01L31/18 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： The composition for forming an n-type diffusion layer in accordance with the present invention contains a glass powder and a dispersion medium, in which the glass powder includes an donor element and a total amount of the life time killer element in the glass powder is 1000 ppm or less. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
摘要翻译：根据本发明的用于形成n型扩散层的组合物含有玻璃粉末和分散介质，其中玻璃粉末包括施主元素，玻璃粉末中的寿命杀伤元素的总量为1000 ppm以下。通过施加用于形成n型扩散层的组合物，然后进行热扩散处理，制备n型扩散层和具有n型扩散层的光伏电池。

90. 发明申请

US20140080294A1 Method for Manufacturing a Semiconductor Structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20140080294A1
公开(公告)日：2014-03-20
申请号：US14086144
申请日：2013-11-21
申请人： Infineon Technologies Austria AG
发明人： Mathias Plappert , Hans-Joachim Schulze
IPC分类号： H01L21/02
CPC分类号： H01L21/02595 , H01L21/02532 , H01L21/02592 , H01L21/02598 , H01L21/02609 , H01L21/02667 , H01L21/04 , H01L21/187 , H01L21/265 , H01L21/28 , H01L21/324 , H01L29/04 , H01L29/43 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
摘要翻译：根据实施例，一种制造半导体结构的方法包括提供在参考方向上具有第一晶格常数的第一单晶半导体部分，并形成在参考方向上具有第二晶格常数的第二单晶半导体部分，其与第一晶格常数，在第一单晶半导体部分上。

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