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81. 发明申请

US20120016650A1 Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System 有权
标题翻译：模拟计算机系统中信号的传输和同时切换输出噪声
公开(公告)号：US20120016650A1
公开(公告)日：2012-01-19
申请号：US12838120
申请日：2010-07-16
申请人： Timothy M. Hollis
发明人： Timothy M. Hollis
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/10 , G06F2217/82
摘要： Methods implementable in a computer system for simulating the transmission of signals across a plurality of data channels (bus) are disclosed. The disclosed techniques simulate the effects of Intersymbol Interference (ISI), cross talk, and Simultaneous Switching Output (SSO) noise by generating Probability Distribution Functions (PDFs) for each. The resulting PDFs are convolved to arrive at a total PDF indicative of the reception of data subject to each of these non-idealities. The total PDF, and its underlying terms, can be indexed to particular channels of the bus as well as to particular logic states. Use of the disclosed technique allows bit error rates and sensing margins to be determined with minimal computation and simulation.
摘要翻译：公开了在用于模拟跨多个数据信道（总线）上的信号传输的计算机系统中可实现的方法。所公开的技术通过产生每个的概率分布函数（PDF）来模拟符号间干扰（ISI），串扰和同时切换输出（SSO）噪声的影响。所得到的PDF被卷积以得到指示接收每个这些非理想性的数据的总的PDF。总的PDF及其基本术语可以索引到总线的特定通道以及特定的逻辑状态。使用所公开的技术允许通过最少的计算和模拟来确定误码率和感测裕度。

82. 发明授权

US08073667B2 System and method for using first-principles simulation to control a semiconductor manufacturing process 有权
标题翻译：使用第一原理模拟来控制半导体制造工艺的系统和方法
公开(公告)号：US08073667B2
公开(公告)日：2011-12-06
申请号：US10673507
申请日：2003-09-30
申请人： Eric J. Strang , Andrej Mitrovic
发明人： Eric J. Strang , Andrej Mitrovic
IPC分类号： G06F17/50 , G06F19/00 , G06G7/48 , H01L21/00
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A method, system and computer readable medium for controlling a process performed by a semiconductor processing tool includes inputting data relating to a process performed by the semiconductor processing tool, and inputting a first principles physical model relating to the semiconductor processing tool. First principles simulation is then performed using the input data and the physical model to provide a first principles simulation result, and the first principles simulation result is used to control the process performed by the semiconductor processing tool.
摘要翻译：用于控制由半导体处理工具执行的处理的方法，系统和计算机可读介质包括输入与由半导体处理工具执行的处理相关的数据，以及输入与半导体处理工具相关的第一原理物理模型。然后使用输入数据和物理模型执行第一原理模拟以提供第一原理模拟结果，并且第一原理模拟结果用于控制由半导体处理工具执行的处理。

83. 发明授权

US08073658B2 Monte Carlo simulation using GPU units on personal computers 有权
标题翻译：在个人电脑上使用GPU单元进行蒙特卡罗模拟
公开(公告)号：US08073658B2
公开(公告)日：2011-12-06
申请号：US11810297
申请日：2007-06-05
申请人： Kirk Gossage
发明人： Kirk Gossage
IPC分类号： G06F7/60 , G06F17/10
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method of performing a Monte Carlo analysis uses a graphical processor unit of a computer system, individual data sets to be analyzed are allocated to respective pixel locations in a graphical processor unit memory for Monte Carlo simulation and the outcome of the Monte Carlo simulation is calculated for each data set using stream processing in the graphical processor unit.
摘要翻译：执行蒙特卡罗分析的方法使用计算机系统的图形处理器单元，将要分析的各个数据集分配给用于蒙特卡洛模拟的图形处理器单元存储器中的各个像素位置，并计算蒙特卡罗模拟的结果对于使用图形处理器单元中的流处理的每个数据集。

84. 发明申请

US20110246811A1 METHOD FOR ESTIMATING THE RELIABILITY OF AN ELECTRONIC CIRCUIT, CORRESPONDING COMPUTERIZED SYSTEM AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：评估电子电路可靠性，相关计算机系统和计算机程序产品的可靠性的方法
公开(公告)号：US20110246811A1
公开(公告)日：2011-10-06
申请号：US13074204
申请日：2011-03-29
申请人： Josep Torras Flaquer , Jean-Marc Daveau , Lirida Naviner , Philippe Roche
发明人： Josep Torras Flaquer , Jean-Marc Daveau , Lirida Naviner , Philippe Roche
IPC分类号： G06F11/00
CPC分类号： G06F11/008 , G06F17/50 , G06F2217/10
摘要： The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component.
摘要翻译：确定具有包括相关源和信宿之间的至少一个再会聚路径的分量节点网络的电子电路的可靠性指南涉及路径的每个分量的水平，条件概率矩阵的计算，其条件概率矩阵的调节与位于组件上游的路径的至少一个节点相关。

85. 发明授权

US08001515B2 Simultaneous optimization of analog design parameters using a cost function of responses 有权
标题翻译：使用响应的成本函数同时优化模拟设计参数
公开(公告)号：US08001515B2
公开(公告)日：2011-08-16
申请号：US12004862
申请日：2007-12-21
申请人： Jang Dae Kim
发明人： Jang Dae Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/08 , G06F2217/10 , G06F2217/16
摘要： An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up the optimization. The cost function compares the behavior of a design to a quantitative specification, which can be a ‘golden’ reference behavior (specification), and measures the error cost, an index of the behavioral discrepancy. That is, the target behavior is explicitly embedded in the cost function. By using the cost function, one can readily qualify a design and thereby identify good/optimum designs. The cost surface modeling with a Latin Hypercube Sampling design-of-experiment provides a statistical mathematical approximation of the actual design's error cost surface, speeding up the optimization by replacing the costly simulation of the actual design with mere evaluation of the mathematical cost surface model expression.
摘要翻译：模拟系统由多个互连组件组成。这种系统的设计涉及组件参数的优化以实现目标行为，统称为规范。本发明提供了用于模拟设计优化的通用成本函数。它还提供成本表面建模以加快优化。成本函数将设计的行为与定量规范进行比较，这可以是“黄金”参考行为（规范），并测量错误成本，这是行为差异的指标。也就是说，目标行为被明确地嵌入到成本函数中。通过使用成本函数，可以很容易地对设计进行限定，从而确定良好/最佳设计。拉丁超立方体采样设计实验的成本表面建模提供了实际设计的误差成本面的统计学数学近似，通过仅仅评估数学成本表面模型表达式代替实际设计的昂贵模拟来加快优化速度。

86. 发明授权

US07992114B1 Timing analysis using statistical on-chip variation 有权
标题翻译：使用统计片上变化的时序分析
公开(公告)号：US07992114B1
公开(公告)日：2011-08-02
申请号：US12135031
申请日：2008-08-19
申请人： Amzie Adams , Alessandra Nardi
发明人： Amzie Adams , Alessandra Nardi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.
摘要翻译：用于时序分析的统计片上变化方法允许自动或半自动选择设计特定的边距，而不需要复杂的统计库。通过单独解决随机和系统变化对时序的影响，可以获得设计特定的余量并在下游OCV分析中使用。此外，在设计的某些部分可以使用统计库的情况下，这些可以逐步包含在时序分析中，以获得更准确的结果。

87. 发明授权

US07991215B2 Element splitting method, element splitting arithmetic device and damage extension analysis device 有权
标题翻译：元素分割方法，元素分割算法装置和损伤扩展分析装置
公开(公告)号：US07991215B2
公开(公告)日：2011-08-02
申请号：US11811896
申请日：2007-06-12
申请人： Tomonaga Okabe , Hideki Sekine , Toshimichi Ogisu
发明人： Tomonaga Okabe , Hideki Sekine , Toshimichi Ogisu
IPC分类号： G06K9/00 , H04N7/18 , H04N9/47 , G06F17/10 , G06F7/60 , G06T15/00 , G06T17/00
CPC分类号： G06F17/5018 , G06F2217/10
摘要： An element splitting method to be applied to a finite element analysis. The method includes: splitting the object region by a Delaunay triangulation by using the coordinate of the point on the boundary line, as a nodal point; disposing circles not to intersect with one another, in the object region, by a Monte Carlo method, the Lawson's search algorithm and a predetermined function; provisionally moving the center coordinate of the one circle by specifying six circles having minimum intervals from one circle by the Monte Carlo method, to adopt the center coordinate after movement when the value of the degree of dispersion Φ after the movement falls below that before the movement; and splitting the object region by a Delaunay triangulation by using the coordinate of the point on the boundary line and the center coordinate, as nodal points.
摘要翻译：一种应用于有限元分析的元素分割方法。该方法包括：通过使用边界线上的点的坐标作为节点将Delaunay三角剖分的对象区域分割; 在对象区域中，通过蒙特卡洛法，Lawson搜索算法和预定函数来设置圈不相交，通过蒙特卡罗方法从一个圆圈中规定具有最小间隔的六个圆圈来暂时移动一个圆的中心坐标，当移动后的分散度Φ的值低于运动之前的分散度Φ的值时，采用运动后的中心坐标 ; 通过使用边界线和中心坐标上的点的坐标作为节点，通过Delaunay三角剖分来分割对象区域。

88. 发明申请

US20110184702A1 Identifying the Defective Layer of a Yield Excursion Through the Statistical Analysis of Scan Diagnosis Results 审中-公开
标题翻译：通过扫描诊断结果的统计分析识别产量偏移的缺陷层
公开(公告)号：US20110184702A1
公开(公告)日：2011-07-28
申请号：US12918984
申请日：2009-02-23
申请人： Manish Sharma , Robert Benware
发明人： Manish Sharma , Robert Benware
IPC分类号： G06F15/00
CPC分类号： G06F17/5081 , G06F2217/10
摘要： Yield excursions in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. Techniques are disclosed herein for efficiently identifying the root-cause of a manufacturing yield excursion by analyzing fail data collected from the production test environment. In particular, statistical hypothesis testing is used in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the cause of the yield excursion.
摘要翻译：今天的制造过程中的产量偏差需要昂贵的，冗长乏味的物理故障分析过程来识别根本原因。本文公开了通过分析从生产测试环境收集的失败数据来有效地识别制造产量偏移的根本原因的技术。特别是以分析逻辑诊断数据以及设计布局中的物理特征信息的新颖方式使用统计假设检验，并可靠地识别产量偏移的原因。

89. 发明申请

US20110173577A1 Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields 审中-公开
标题翻译：用于最大化过程敏感电路产量的模式过程调优和设计优化技术
公开(公告)号：US20110173577A1
公开(公告)日：2011-07-14
申请号：US12024390
申请日：2008-02-01
申请人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
发明人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.
摘要翻译：提供了改进电路设计和生产的技术。一方面，提供了一种用于虚拟制造过程敏感电路的方法。该方法包括以下步骤。基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。基于质量的度量用于为制造的电路的虚拟表示投影产量。物理布局图和/或生产过程被修改。重复获得，使用和修改步骤，直到达到期望的预计产量。

90. 发明授权

US07937679B2 Method for performing failure mode and effects analysis of an integrated circuit and computer program product therefor 有权
标题翻译：用于执行集成电路及其计算机程序产品的故障模式和效果分析的方法
公开(公告)号：US07937679B2
公开(公告)日：2011-05-03
申请号：US12101585
申请日：2008-04-11
申请人： Riccardo Mariani
发明人： Riccardo Mariani
IPC分类号： G06F17/50 , G06F9/455 , G06F11/00
CPC分类号： G06F11/2252 , G01R31/2846 , G06F17/5022 , G06F2217/10 , G06F2217/70 , Y02T10/82
摘要： A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results.
摘要翻译：一种用于在集成电路上执行故障模式和效果分析（FMEA）的方法，包括准备FMEA数据库中设计的集成电路的FMEA数据库和计算FMEA结果。从集成电路描述中自动提取信息。信息的提取包括使用FMEA数据库的准备步骤中的信息来读取集成电路信息，在不变和基本敏感区（SZ）中分割电路。可选地，可以执行FMEA验证阶段，将FMEA计算结果与FMEA测量结果进行比较以获得FMEA验证结果。

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