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1. 发明申请

US20110173577A1 Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields 审中-公开
标题翻译：用于最大化过程敏感电路产量的模式过程调优和设计优化技术
公开(公告)号：US20110173577A1
公开(公告)日：2011-07-14
申请号：US12024390
申请日：2008-02-01
申请人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
发明人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.
摘要翻译：提供了改进电路设计和生产的技术。一方面，提供了一种用于虚拟制造过程敏感电路的方法。该方法包括以下步骤。基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。基于质量的度量用于为制造的电路的虚拟表示投影产量。物理布局图和/或生产过程被修改。重复获得，使用和修改步骤，直到达到期望的预计产量。

2. 发明授权

US07751267B2 Half-select compliant memory cell precharge circuit 有权
标题翻译：半选择兼容的存储单元预充电电路
公开(公告)号：US07751267B2
公开(公告)日：2010-07-06
申请号：US11782071
申请日：2007-07-24
申请人： Rajiv V. Joshi , Rouwaida Kanj , Jayakumaran Sivagnaname
发明人： Rajiv V. Joshi , Rouwaida Kanj , Jayakumaran Sivagnaname
IPC分类号： G11C7/12 , G11C11/41 , G11C11/413
CPC分类号： G11C7/12 , G11C11/412
摘要： A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors.
摘要翻译：可编程预充电电路包括多个晶体管。每个晶体管具有与多个晶体管中的其它晶体管不同的阈值电压。每个晶体管被配置为将电源电压连接到节点，并且根据存储器操作将节点选择性地耦合到位线。控制逻辑被配置为使得多个晶体管中的至少一个能够根据来自多个晶体管之一的电源电压的相应阈值电压降向节点提供可编程的预充电电压。

3. 发明申请

US20090027983A1 HALF-SELECT COMPLIANT MEMORY CELL PRECHARGE CIRCUIT 有权
标题翻译：半选择合规存储器单元预充电路
公开(公告)号：US20090027983A1
公开(公告)日：2009-01-29
申请号：US11782071
申请日：2007-07-24
申请人： Rajiv V. Joshi , Rouwaida Kanj , Jayakumaran Sivagnaname
发明人： Rajiv V. Joshi , Rouwaida Kanj , Jayakumaran Sivagnaname
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/412
摘要： A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors.
摘要翻译：可编程预充电电路包括多个晶体管。每个晶体管具有与多个晶体管中的其它晶体管不同的阈值电压。每个晶体管被配置为将电源电压连接到节点，并且根据存储器操作将节点选择性地耦合到位线。控制逻辑被配置为使得多个晶体管中的至少一个能够根据来自多个晶体管之一的电源电压的相应阈值电压降向节点提供可编程的预充电电压。

4. 发明申请

US20070220455A1 Method and computer program for efficient cell failure rate estimation in cell arrays 有权
标题翻译：用于单元阵列中有效单元故障率估计的方法和计算机程序
公开(公告)号：US20070220455A1
公开(公告)日：2007-09-20
申请号：US11375477
申请日：2006-03-14
申请人： Rajiv Joshi , Rouwaida Kanj , Sani Nassif
发明人： Rajiv Joshi , Rouwaida Kanj , Sani Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G11C29/028 , G11C29/54 , G11C29/56004 , G11C29/56008 , G11C2029/0403
摘要： A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.
摘要翻译：用于在单元阵列中有效的单元故障率估计的方法和计算机程序提供了一种有效的机制，用于提高存储器阵列的性能超过现有水平/产量。在单元电路参数之间执行初始搜索以确定关于一组性能变量的故障。对于单个故障区域，初始搜索可以是参数空间的均匀采样，并且当已经累积了足够的故障点时，从检测到的故障点的平均值中选择一个平均值。然后执行混合重要性采样（MIS）以有效地估计单个故障区域。对于多个故障区域，通过沿随机矢量集改变存储器电路单元参数直到检测到故障来选择特定故障区域，从而将感兴趣的故障区域的边界识别为最接近的故障区域。根据检测到的边界的位置，为MIS选择新的平均值。

5. 发明授权

US08170857B2 In-situ design method and system for improved memory yield 有权
标题翻译：提高记忆产量的原位设计方法和系统
公开(公告)号：US08170857B2
公开(公告)日：2012-05-01
申请号：US12324170
申请日：2008-11-26
申请人： Rajiv V. Joshi , Rouwaida Kanj
发明人： Rajiv V. Joshi , Rouwaida Kanj
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/10 , G06F2217/12 , G11C11/412 , Y02P90/265
摘要： A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.
摘要翻译：用于设计集成电路的系统和方法包括通过评估存储器模块的性能变量来确定用于评估和改进的目标存储器模块。基于模块的引脚信息，对变量的子集组合对性能变量进行统计学模拟。确定在子集合中变量对产量的收益的敏感度。然后确定目标模块的产量是否可接受，并且如果产量不可接受，则根据敏感度调整包括目标模块的设计以调整产量。

6. 发明申请

US20100131259A1 IN-SITU DESIGN METHOD AND SYSTEM FOR IMPROVED MEMORY YIELD 有权
标题翻译：改进的存储器的现场设计方法和系统
公开(公告)号：US20100131259A1
公开(公告)日：2010-05-27
申请号：US12324170
申请日：2008-11-26
申请人： Rajiv V. Joshi , Rouwaida Kanj
发明人： Rajiv V. Joshi , Rouwaida Kanj
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/10 , G06F2217/12 , G11C11/412 , Y02P90/265
摘要： A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.
摘要翻译：用于设计集成电路的系统和方法包括通过评估存储器模块的性能变量来确定用于评估和改进的目标存储器模块。基于模块的引脚信息，对变量的子集组合对性能变量进行统计学模拟。确定在子集合中变量对产量的收益的敏感度。然后确定目标模块的产量是否可接受，并且如果产量不可接受，则根据敏感度调整包括目标模块的设计以调整产量。

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