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81. 发明授权

US09311228B2 Power reduction in server memory system 有权
标题翻译：服务器内存系统功耗降低
公开(公告)号：US09311228B2
公开(公告)日：2016-04-12
申请号：US13439457
申请日：2012-04-04
申请人： David M. Daly , Tejas Karkhanis , Valentina Salapura
发明人： David M. Daly , Tejas Karkhanis , Valentina Salapura
IPC分类号： G06F12/00 , G06F12/02 , G06F11/34 , G06F12/06
CPC分类号： G06F12/023 , G06F11/3409 , G06F11/3471 , G06F12/06 , G06F2201/81 , G06F2201/88 , G06F2212/1028 , G06F2212/2532 , G06F2212/502 , Y02D10/13 , Y02D10/34
摘要： A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
摘要翻译：一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法，其经由存储器控制器与存储器芯片无效通信。存储器可以以模式操作，使得经由存储器控制器，存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动，从而导致更少的操作等级。然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。

82. 发明授权

US09311098B2 Mechanism for reducing cache power consumption using cache way prediction 有权
标题翻译：使用缓存方式预测降低缓存功耗的机制
公开(公告)号：US09311098B2
公开(公告)日：2016-04-12
申请号：US13888551
申请日：2013-05-07
申请人： Apple Inc.
发明人： Ronald P. Hall , Conrado Blasco-Allue
IPC分类号： G06F12/00 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3806 , G06F9/3838 , G06F12/0864 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored.
摘要翻译：用于降低处理器的高速缓冲存储器的功耗的机构包括具有高速缓存存储器的处理器，该高速缓冲存储器存储从系统存储器取出的一个或多个指令获取组的指令信息。高速缓冲存储器可以包括各自独立可控的多种方式。处理器还包括方式预测单元。方式预测单元可以在下一个执行周期中使得响应于下一个分支指令的分支采取预测而存储对应于下一分支指令的目标的指令信息的给定方式。方式预测单元还可以响应于对下一个分支指令的分支采取的预测，一次一个地使能存储与下一个分支指令之后的各个顺序指令获取组对应的指令信息的每个对应方式。

83. 发明申请

US20160092372A1 READ CACHE MANAGEMENT IN MULTI-LEVEL CELL (MLC) NON-VOLATILE MEMORY 有权
标题翻译：读取多级存储器（MLC）非易失性存储器中的缓存管理
公开(公告)号：US20160092372A1
公开(公告)日：2016-03-31
申请号：US14499286
申请日：2014-09-29
申请人： APPLE INC.
发明人： Alex Radinski , Tsafrir Kamelo
IPC分类号： G06F12/12
CPC分类号： G06F12/121 , G06F12/0868 , G06F2212/1021 , G06F2212/1024 , G06F2212/1028 , G06F2212/214 , G06F2212/312 , G11C11/5642 , G11C2211/5641 , Y02D10/13
摘要： A method includes reading memory pages from a non-volatile memory that holds at least first memory pages having a first bit significance and second memory pages having a second bit significance, different from the first bit significance. At least some of the read memory pages are cached in a cache memory. One or more of the cached memory pages are selected for eviction from the cache memory, in accordance with a selection criterion that gives eviction preference to the memory pages of the second bit significance over the memory pages of the first bit significance. The selected memory pages are evicted from the cache memory.
摘要翻译：一种方法包括从非易失性存储器读取存储器页面，该存储器页面至少保存具有第一位重要性的第一存储器页面和不同于第一位重要性的具有第二位重要性的第二存储器页面。至少一些读取的存储器页面被缓存在高速缓冲存储器中。根据对第一位有效位的存储器页上的第二位有效位的存储器页进行逐出偏好的选择标准，选择一个或多个高速缓冲存储器页面用于从高速缓冲存储器进行驱逐。所选存储器页被从缓存存储器中逐出。

84. 发明授权

US09298615B2 Methods and apparatus for soft-partitioning of a data cache for stack data 有权
标题翻译：用于堆栈数据的数据缓存的软分区的方法和装置
公开(公告)号：US09298615B2
公开(公告)日：2016-03-29
申请号：US13946112
申请日：2013-07-19
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Lena E. Olson , Yasuko Eckert , Vilas K. Sridharan , James M. O'Connor , Mark D. Hill , Srilatha Manne
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0802 , G06F12/0848 , G06F12/0862 , G06F12/0864 , G06F12/0875 , G06F12/123 , G06F2212/1016 , G06F2212/1028 , G06F2212/451 , G06F2212/502 , G06F2212/601 , G06F2212/6032 , G06F2212/6082 , Y02D10/13
摘要： A method of partitioning a data cache comprising a plurality of sets, the plurality of sets comprising a plurality of ways, is provided. Responsive to a stack data request, the method stores a cache line associated with the stack data in one of a plurality of designated ways of the data cache, wherein the plurality of designated ways is configured to store all requested stack data.
摘要翻译：提供了一种分割包括多个集合的数据高速缓存的方法，所述多个集合包括多个方式。响应于堆栈数据请求，该方法将与堆栈数据相关联的高速缓存行存储在数据高速缓存的多个指定方式之一中，其中多个指定路径被配置为存储所有请求的堆栈数据。

85. 发明申请

US20160070505A1 EFFICIENT LOADING AND STORING OF DATA 有权
标题翻译：有效加载和存储数据
公开(公告)号：US20160070505A1
公开(公告)日：2016-03-10
申请号：US14847681
申请日：2015-09-08
申请人： Imagination Technologies Limited
发明人： Michael John Davis , Adrian John Anderson , Gary Christopher Wass
IPC分类号： G06F3/06
CPC分类号： G06F3/0638 , G06F3/061 , G06F3/0673 , G06F9/30043 , G06F9/34 , G06F9/38 , G06F9/3824 , G06F12/02 , G06F12/0207 , G06F2212/1028 , G06F2212/1041 , Y02D10/13
摘要： Methods and apparatus for efficient loading of data from memory to registers and storing of data from registers to memory are described. In an embodiment, a processor comprises a data structure to which addresses which are used for load operations are pushed. Instead of independently generating addresses for a store operation, addresses are popped from the data structure and either used directly or an optional offset may first be applied to the popped address. In this way, a store operation and a load operation may be performed in parallel because they do not both require use of the logic which independently generates addresses for load/store operations. In various examples, the data structure is a FIFO structure.
摘要翻译：描述了将数据从存储器有效地加载到寄存器并将数据从寄存器存储到存储器的方法和装置。在一个实施例中，处理器包括被推送用于加载操作的地址的数据结构。不是独立地生成用于存储操作的地址，而是从数据结构中弹出地址，并直接使用地址，或者可以首先将可选的偏移应用于弹出的地址。以这种方式，可以并行执行存储操作和加载操作，因为它们不需要使用独立地生成用于加载/存储操作的地址的逻辑。在各种示例中，数据结构是FIFO结构。

86. 发明申请

US20150357025A1 DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION 有权
公开(公告)号：US20150357025A1
公开(公告)日：2015-12-10
申请号：US14711581
申请日：2015-05-13
申请人： Intel Corporation
发明人： Jim Kardach , Nikos Kaburlasos
IPC分类号： G11C11/406 , G11C7/10
CPC分类号： G11C11/40618 , G06F12/0223 , G06F12/06 , G06F12/0607 , G06F2212/1028 , G11C7/1072 , G11C11/406 , G11C11/40622 , Y02D10/13
摘要： Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.

87. 发明申请

US20150309934A1 ARITHMETIC PROCESSING APPARATUS AND METHOD FOR CONTROLLING SAME 有权
标题翻译：算术处理装置及其控制方法
公开(公告)号：US20150309934A1
公开(公告)日：2015-10-29
申请号：US14672284
申请日：2015-03-30
申请人： FUJITSU LIMITED
发明人： Ryuichi SUNAYAMA
IPC分类号： G06F12/08
CPC分类号： G06F12/0607 , G06F12/0811 , G06F12/0826 , G06F2212/1024 , G06F2212/1028 , Y02D10/13
摘要： An arithmetic processing apparatus includes: first and second core groups each including cores, a first to an Nth (N is plural) caches that process access requests from the cores, and an intra-core-group bus through which the access requests from the cores are provided to the first to Nth caches; and a first to an Nth inter-core-group buses each provided between the first to Nth caches in the first and second core groups respectively. The first to Nth caches in the first core group individually store data from a first to an Nth memory spaces in a memory, respectively. The first to Nth caches in the second core group individually store data from an N+1th to a 2Nth memory spaces, respectively. The first to Nth caches in the first core group access the data in the N+1th to 2Nth memory spaces, respectively, via the first to Nth inter-core-group buses.
摘要翻译：算术处理装置包括：第一和第二核心组，每个核心组包括核心，处理来自核心的访问请求的第一至第N（N个是多个）高速缓存，以及核心组总线，通过该核心组从核心访问请求提供给第一至第N个缓存; 以及分别设置在第一和第二核心组中的第一至第N个高速缓存之间的第一至第N个核心间总线总线。第一核心组中的第一至第N个高速缓存分别存储来自存储器中的第一至第N个存储空间的数据。第二核心组中的第一至第N个高速缓存分别将从N + 1到第2N个存储空间的数据分别存储。第一核心组中第一至第N个高速缓存通过第一至第N个核心间总线分别访问第N + 1至第2N个存储空间中的数据。

88. 发明授权

US09170947B2 Recovering from data errors using implicit redundancy 有权
标题翻译：使用隐式冗余从数据错误中恢复
公开(公告)号：US09170947B2
公开(公告)日：2015-10-27
申请号：US13992732
申请日：2011-12-29
申请人： Xavier Vera , Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez
发明人： Xavier Vera , Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez
IPC分类号： G06F13/00 , G06F12/08 , G06F11/00 , G06F11/08 , G06F11/16 , G06F12/12 , G06F11/20
CPC分类号： G06F12/0822 , G06F11/00 , G06F11/08 , G06F11/1666 , G06F11/20 , G06F12/0806 , G06F12/0815 , G06F12/0817 , G06F12/12 , G06F2212/1024 , G06F2212/1028 , G06F2212/1044 , Y02D10/13
摘要： Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.
摘要翻译：本文公开的一些实现方式提供了通过存储在高速缓存目录中的信息来恢复存储在由多个处理器共享的存储器中的数据的技术和装置。处理器的核心可以启动对位于核心可访问的第一高速缓存中的特定数据的访问（例如，读或写）。响应于检测到与访问特定数据相关联的错误，可以识别包括特定数据的处理器中的位置，并且可以将特定数据从该位置复制到第一高速缓存。

89. 发明申请

US20150286578A1 MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION 审中-公开
公开(公告)号：US20150286578A1
公开(公告)日：2015-10-08
申请号：US14742809
申请日：2015-06-18
申请人： Moon J. Kim
发明人： Moon J. Kim
IPC分类号： G06F12/10 , G06F13/16 , G06F13/42
CPC分类号： G06F12/1081 , G06F1/3287 , G06F12/0284 , G06F12/06 , G06F12/08 , G06F13/1694 , G06F13/28 , G06F13/4234 , G06F2212/1028 , G06F2212/2532 , Y02D10/13 , Y02D10/151 , Y02D10/171
摘要： Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

90. 发明申请

US20150279464A1 MANAGED RUNTIME EXTENSIONS TO REDUCE POWER CONSUMPTION IN DEVICES WITH HYBRID MEMORY 有权
标题翻译：管理的运行延伸，以减少设备中的消耗功率与混合存储器
公开(公告)号：US20150279464A1
公开(公告)日：2015-10-01
申请号：US14227432
申请日：2014-03-27
申请人： Stephan A. Herhut , Richard L. Hudson , Tatiana Shpeisman
发明人： Stephan A. Herhut , Richard L. Hudson , Tatiana Shpeisman
IPC分类号： G11C14/00 , G06F12/02
CPC分类号： G06F12/0276 , G06F12/0238 , G06F2212/1028 , G06F2212/1041 , G06F2212/205 , G06F2212/7202 , G06F2212/7205 , Y02D10/13
摘要： Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.
摘要翻译：系统和方法可以提供用于识别被管理的运行时环境中的对象并且在所管理的运行时环境的软件级别确定对象的年龄。另外，可以至少部分地基于对象的年龄，将对象选择性地分配在动态随机存取存储器（DRAM）或非易失性随机存取存储器（NVRAM）之一中。在一个示例中，还确定对象的数据类型，其中基于数据类型有选择地分配对象。

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