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81. 发明申请

US20010027516A1 Squence control circuit 有权
标题翻译：排气控制电路
公开(公告)号：US20010027516A1
公开(公告)日：2001-10-04
申请号：US09816338
申请日：2001-03-26
发明人： Futoshi Kawarazaki
IPC分类号： G06F009/00
CPC分类号： G06F9/3804 , G01R31/31921 , G06F9/322 , G11C29/56
摘要： A sequence control circuit that is capable of operating at high-speed without using either a memory having a short access time or high-speed devices is provided. Each address of an instruction memory includes an instruction next to the current instruction designated by a program counter signal and an instruction of the jump target of the current instruction. Instruction registers receive instructions from the instruction memory to output those in the next cycle. A selector selects either one of the outputs from the instruction registers depending on a jump signal. A program counter control section decodes an instruction from the selector to determine the next program counter signal and a jump signal. An address register receives the next program counter signal to output an instruction memory address in the next cycle. A jump register receives the jump signal to output that to the selector in the next cycle.
摘要翻译：提供了一种能够在不使用具有短访问时间的存储器或高速设备的情况下以高速操作的顺序控制电路。指令存储器的每个地址包括由程序计数器信号指定的当前指令旁边的指令和当前指令的跳转目标的指令。指令寄存器从指令存储器接收指令，以在下一个周期中输出指令。选择器根据跳转信号从指令寄存器中选择一个输出。程序计数器控制部分对来自选择器的指令进行解码，以确定下一个程序计数器信号和跳转信号。地址寄存器接收下一个程序计数器信号，以在下一个周期中输出指令存储器地址。跳转寄存器接收跳转信号，以在下一个周期中将其输出到选择器。

82. 发明授权

US06202187B1 Pattern generator for use in a semiconductor test device 失效
标题翻译：用于半导体测试装置的图案发生器
公开(公告)号：US06202187B1
公开(公告)日：2001-03-13
申请号：US09127537
申请日：1998-07-31
申请人： Tsumtomu Akiyama
发明人： Tsumtomu Akiyama
IPC分类号： G01R3128
CPC分类号： G01R31/318385 , G01R31/31813 , G01R31/31921
摘要： A pattern generator for use in a semiconductor test device provided with a random access memory which has large capacity and runs at high speed and is capable of generating random pattern data having large capacity and running at high speed. Parts of random pattern data previously stored in a sequential pattern memory are transferred to addresses of a random pattern memory which are specified by the difference calculated by an arithmetic circuit between address data outputted from a control circuit and address data outputted from an address generator, and the transferred random pattern data are outputted to a semiconductor to be tested through a selection circuit.
摘要翻译：一种用于半导体测试装置的模式发生器，该半导体测试装置具有大容量且高速运行的随机存取存储器，能够产生大容量并高速运行的随机模式数据。先前存储在顺序模式存储器中的随机模式数据的部分被传送到随机模式存储器的地址，这些地址由运算电路在从控制电路输出的地址数据和从地址生成器输出的地址数据之间计算的差指定，传输的随机图案数据通过选择电路输出到要测试的半导体。

83. 发明授权

US6107818A High speed, real-time, state interconnect for automatic test equipment 失效
标题翻译：用于自动测试设备的高速，实时，状态互连
公开(公告)号：US6107818A
公开(公告)日：2000-08-22
申请号：US60987
申请日：1998-04-15
申请人： Allen J. Czamara
发明人： Allen J. Czamara
IPC分类号： G01R31/28 , G01R31/3167 , G01R31/319 , G01R31/26 , G01R31/3181
CPC分类号： G01R31/31921 , G01R31/31907 , G01R31/3191 , G01R31/3167
摘要： A tester is disclosed in which state coherency is maintained between functional blocks of the tester by way of a novel state distribution and recombination network. The network includes a plurality of nodes configured to provide point-to-point links between pairs of functional blocks. Further, time delays through the point-to-point links can be adjusted by selecting a suitable node configuration and by programming delay circuitry included in each node. The network therefore maintains state coherence between the functional blocks by ensuring that delays throughout the test system are both deterministic and adjustable. The tester is particularly useful for testing complex, mixed-signal semiconductor devices.
摘要翻译：公开了一种测试器，其中通过新的状态分布和重组网络在测试仪的功能块之间维持状态一致性。网络包括多个节点，被配置为提供功能块对之间的点对点链路。此外，可以通过选择合适的节点配置并通过编程包括在每个节点中的延迟电路来调整通过点对点链路的时间延迟。因此，网络通过确保整个测试系统中的延迟都是确定性的和可调节的来维持功能块之间的状态一致性。该测试仪特别适用于测试复杂的混合信号半导体器件。

84. 发明授权

US6067648A Programmable pulse generator 失效
标题翻译：可编程脉冲发生器
公开(公告)号：US6067648A
公开(公告)日：2000-05-23
申请号：US32968
申请日：1998-03-02
申请人： Paul R. Hunter , Archer R. Lawrence , Jack C. Little
发明人： Paul R. Hunter , Archer R. Lawrence , Jack C. Little
IPC分类号： G01R31/319 , G11C29/56 , H03K5/15 , G11C29/00 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1502 , G11C29/56 , G01R31/31921
摘要： A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.
摘要翻译：数字可编程延迟，提供一系列以脉冲延迟和触发延迟编程的脉冲，以控制存储器模块测试系统的操作。

85. 发明授权

US6014764A Providing test vectors with pattern chaining definition 失效
标题翻译：提供带有模式链接定义的测试向量
公开(公告)号：US6014764A
公开(公告)日：2000-01-11
申请号：US858992
申请日：1997-05-20
申请人： Egbert Graeve , Burnell G. West , Teck Chiau Chew
发明人： Egbert Graeve , Burnell G. West , Teck Chiau Chew
IPC分类号： G01R31/3183 , G01R31/319 , G06F11/22 , G01R31/28
CPC分类号： G01R31/31921
摘要： Apparatus and methods providing pattern chaining and looping in a circuit tester. The tester has a pattern data memory for storing multiple patterns and for storing a pattern chaining definition. Each pattern has pattern data for one or more test vectors. The pattern chaining definition specifies (i) a sequential order for the patterns and (ii) a location in the pattern data memory of each of the patterns. When the tester executes a functional test, the pattern chaining definition is read from the pattern data memory and used to locate each of the patterns, and the pattern data of each pattern is read to provide a test vector for each test period of the functional test. In another aspect, both a pattern program including one or more test vectors and a loop definition are stored in the pattern data memory. The pattern program defines an ordering for the test vectors, and the loop definition specifies a loop of test vectors. When the tester executes a functional test that includes the loop, the test vectors of the loop are read an indefinite number of times until a loop ending condition occurs. The first loop test vector of the loop need not be the initial test vector of the pattern program. In another aspect, the tester has chaining control registers including a start address register for pointing to a pattern chaining definition stored in the pattern data memory and a current pattern pointer register for pointing to a current pattern stored in the pattern data memory; a pattern data output sequencer; and a pattern data buffer memory coupled between the pattern data memory and the pattern data output sequencer.
摘要翻译：在电路测试仪中提供模式链接和循环的装置和方法。测试器具有用于存储多个图案并用于存储图案链接定义的图案数据存储器。每个图案具有用于一个或多个测试向量的图案数据。图案链接定义指定（i）图案的顺序，以及（ii）每个图案的图案数据存储器中的位置。当测试者执行功能测试时，从模式数据存储器中读取模式链接定义，并用于定位每个模式，读取每个模式的模式数据，为功能测试的每个测试周期提供一个测试向量。在另一方面，包括一个或多个测试向量和循环定义的模式程序都存储在模式数据存储器中。模式程序定义测试向量的顺序，循环定义指定一个测试向量循环。当测试仪执行包括循环的功能测试时，循环的测试向量将被读取无限次，直到出现循环结束条件。循环的第一个循环测试向量不需要是模式程序的初始测试向量。在另一方面，测试仪具有链接控制寄存器，其包括用于指向存储在模式数据存储器中的模式链接定义的起始地址寄存器和用于指向存储在模式数据存储器中的当前模式的当前模式指针寄存器; 模式数据输出音序器; 以及耦合在图案数据存储器和图案数据输出定序器之间的图案数据缓冲存储器。

86. 发明授权

US5899961A Electronic circuit or board tester with compressed data-sequences 失效
标题翻译：具有压缩数据序列的电子电路或电路板测试仪
公开(公告)号：US5899961A
公开(公告)日：1999-05-04
申请号：US811153
申请日：1997-03-04
申请人： Jens Sundermann
发明人： Jens Sundermann
IPC分类号： G01R31/02 , G01R31/28 , G01R31/3183 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/31921 , G01R31/31935
摘要： This invention relates to electronic circuit testing and more particularly to an apparatus utilizing data compression techniques. An electronic circuit or board tester according to the invention includes one tester circuit with the combination of a sequencer and a vector-sequencer-memory per pin. A data-sequence, such as a loop to address the memory cells of an electronic memory one after the other in a predetermined chronological order, is applied to a pin of a device under test and is compressed in order to save memory space.
摘要翻译：本发明涉及电子电路测试，更具体地说，涉及利用数据压缩技术的设备。根据本发明的电子电路或电路板测试器包括一个测试器电路，每个引脚具有定序器和矢量定序器存储器的组合。一个数据序列，例如以预定的时间顺序将电子存储器的存储单元一个接一个地寻址的循环，被施加到被测设备的引脚上并被压缩以便节省存储器空间。

87. 发明授权

US5835506A Single pass doublet mode integrated circuit tester 失效
标题翻译：单通双模集成电路测试仪
公开(公告)号：US5835506A
公开(公告)日：1998-11-10
申请号：US845942
申请日：1997-04-29
申请人： Philip T. Kuglin
发明人： Philip T. Kuglin
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/31921 , G01R31/31926 , G01R31/3193
摘要： An integrated circuit tester includes a set of pin electronics circuits, each for carrying out a sequence of activities at a separate terminal of a device under test (DUT) in response to an input vector sequence. Such activities may include sending a test signal to the DUT terminal or ascertaining the state of a DUT output signal at the terminal. Each pin electronics circuit can operate in either of two modes, normal and doublet. The test is organized into a set of successive test cycles. When operating in the normal mode, a pin electronics circuit interprets each successive input vector as defining activities to be carried out during a single cycle of the test. When operating in the doublet mode, a pin electronics circuit interprets each successive input vector as defining activities to be carried out during two successive test cycles.
摘要翻译：集成电路测试器包括一组引脚电子电路，每组用于响应于输入矢量序列在待测器件（DUT）的单独端子处执行一系列活动。这样的活动可以包括向DUT终端发送测试信号或者确定终端处的DUT输出信号的状态。每个引脚电子电路可以在正常和双工两种模式中工作。测试被组织成一组连续的测试周期。当在正常模式下操作时，引脚电子电路将每个连续的输入向量解释为在测试的单个周期期间执行的活动。当在双工模式下工作时，引脚电子电路将每个连续的输入矢量解释为定义在两个连续测试周期期间执行的活动。

88. 发明授权

US5825787A System and method for accessing a test vector memory 失效
标题翻译：用于访问测试向量存储器的系统和方法
公开(公告)号：US5825787A
公开(公告)日：1998-10-20
申请号：US978163
申请日：1997-11-25
申请人： Mihai G. Statovici
发明人： Mihai G. Statovici
IPC分类号： G01R31/319 , G06F11/20 , G06F11/00
CPC分类号： G01R31/31921
摘要： An improved circuit tester allows for increased storage of test vectors in existing memory structures by noting where segments of test vectors repeat and storing such segments only once, then further utilizing memory space corresponding to otherwise unused test channels. Switching circuitry is included to selectively forward signals to and from a designated, multi-source conductor.
摘要翻译：改进的电路测试器允许通过注意测试向量的区段重复并存储这些段仅一次，从而进一步利用对应于否则未使用的测试信道的存储器空间来增加现有存储器结构中测试向量的存储。包括开关电路以选择性地将信号转发到指定的多源导体和从指定的多源导体转发信号。

89. 发明授权

US5790411A Equipment for testing electronic circuitry 失效
标题翻译：电子电路测试设备
公开(公告)号：US5790411A
公开(公告)日：1998-08-04
申请号：US740677
申请日：1996-10-31
申请人： Alan John Nelson
发明人： Alan John Nelson
IPC分类号： G01R31/28 , G01R31/319 , G06F11/22
CPC分类号： G01R31/31908 , G01R31/31926 , G01R31/31921
摘要： An equipment for testing electronic circuitry comprising: test connections to said circuitry; measurement means for generating test signals for application to said circuitry and monitoring response signals produced by the circuitry in response to the test signals, said test signals being applied and said response signals being received by way of said test connections; switches for switching the test signals generated to said test connections and the response signals produced to said measurement means; means defining the settings of said switches for a current test of a series of tests required to be performed on said circuitry; first memory means for storing the switch settings for the next test of said series following said current test; second memory means for storing the switch settings for the entire series of tests; and sequencer means for transferring (i) the next switch settings from said first memory means to said means defining and (ii) the switch settings for the test of said series following said next test from said second memory means to said first memory means, said sequencer means initiating the transferring in response to the receipt of a trigger signal from said measurement means indicating that test signals for said next test will be applied to said circuitry after a predetermined time.
摘要翻译：一种用于测试电子电路的设备，包括：与所述电路的测试连接; 测量装置，用于产生用于应用于所述电路的测试信号并且响应于所述测试信号监测由所述电路产生的响应信号，所述测试信号被施加，并且所述响应信号通过所述测试连接被接收; 用于切换产生到所述测试连接的测试信号的开关和对所述测量装置产生的响应信号; 用于定义所述开关的设置用于当前测试需要在所述电路上执行的一系列测试; 第一存储装置，用于存储在所述当前测试之后的所述系列的下一次测试的开关设置; 用于存储整个系列测试的开关设置的第二存储器装置; 以及定序器装置，用于将下一个开关设置从所述第一存储器装置转移到所述装置，以及（ii）在所述第二存储器装置对所述第一存储装置进行的所述下一次测试之后所述串联测试的开关设置，响应于从所述测量装置接收到来自所述测量装置的触发信号，所述定序器意味着启动所述传送，指示在预定时间之后所述下一个测试的测试信号将被施加到所述电路。

90. 发明授权

US5748642A Parallel processing integrated circuit tester 失效
公开(公告)号：US5748642A
公开(公告)日：1998-05-05
申请号：US534015
申请日：1995-09-25
申请人： Gary J. Lesmeister
发明人： Gary J. Lesmeister
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3183 , G01R31/319 , G06F1/025 , G06F1/04
CPC分类号： G01R31/31813 , G01R31/2851 , G01R31/31907 , G01R31/3191 , G01R31/31921 , G01R31/31922 , G06F1/025 , G06F1/04
摘要： An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands. The processing nodes are interconnected in serial fashion to form a network for conveying the algorithmic instructions to the memory of each node and for conveying signals for synchronizing operations of the processing nodes. The nodes contain circuitry to start and stop operations in a unified manner so that the serially connected nodes act as if connected in parallel.

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