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1. 发明授权

US5835506A Single pass doublet mode integrated circuit tester 失效
标题翻译：单通双模集成电路测试仪
公开(公告)号：US5835506A
公开(公告)日：1998-11-10
申请号：US845942
申请日：1997-04-29
申请人： Philip T. Kuglin
发明人： Philip T. Kuglin
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/31921 , G01R31/31926 , G01R31/3193
摘要： An integrated circuit tester includes a set of pin electronics circuits, each for carrying out a sequence of activities at a separate terminal of a device under test (DUT) in response to an input vector sequence. Such activities may include sending a test signal to the DUT terminal or ascertaining the state of a DUT output signal at the terminal. Each pin electronics circuit can operate in either of two modes, normal and doublet. The test is organized into a set of successive test cycles. When operating in the normal mode, a pin electronics circuit interprets each successive input vector as defining activities to be carried out during a single cycle of the test. When operating in the doublet mode, a pin electronics circuit interprets each successive input vector as defining activities to be carried out during two successive test cycles.
摘要翻译：集成电路测试器包括一组引脚电子电路，每组用于响应于输入矢量序列在待测器件（DUT）的单独端子处执行一系列活动。这样的活动可以包括向DUT终端发送测试信号或者确定终端处的DUT输出信号的状态。每个引脚电子电路可以在正常和双工两种模式中工作。测试被组织成一组连续的测试周期。当在正常模式下操作时，引脚电子电路将每个连续的输入向量解释为在测试的单个周期期间执行的活动。当在双工模式下工作时，引脚电子电路将每个连续的输入矢量解释为定义在两个连续测试周期期间执行的活动。

2. 发明授权

US06392404B1 Triggered integrated circuit tester 失效
标题翻译：触发式集成电路测试仪
公开(公告)号：US06392404B1
公开(公告)日：2002-05-21
申请号：US09628703
申请日：2000-07-31
申请人： Philip T. Kuglin
发明人： Philip T. Kuglin
IPC分类号： G01R3126
CPC分类号： G01R31/31922
摘要： A triggered integrated circuit (IC) tester in accordance with the invention organizes a test of an IC into a succession of test cycles. A vector generated prior to the start of each test cycle references the test activities to be carried out during the test cycle. The tester generates a set of N periodic timing signals, T0 through T(N−1), each having a period equal to the duration of one test cycle with the timing signals being distributed in phase so that their edges evenly divide each test cycle into N intervals. Each test cycle nominally starts on an edge of the T0 signal, and each vector referencing a test event also indicates a nominal time delay following the start of the test cycle at which the event is to occur by referencing one of the timing signals T0 through T(N−1). However whenever the tester receives an input trigger signal edge, it determines an offset between the most recent T0 signal edge and the occurrence of the trigger signal edge. During subsequent test cycles, the tester delays the start of test cycles and occurrence of test events by the amount of the trigger signal edge offset. In doing so, the tester makes the delay of each subsequent test event with respect to the trigger signal edge a predictable function of the vector sequence.
摘要翻译：根据本发明的触发式集成电路（IC）测试器将IC的测试组织成一系列测试周期。在每个测试周期开始之前产生的矢量参考在测试周期中要执行的测试活动。测试仪产生一组N个周期性定时信号T0到T（N-1），每个周期定时信号的周期等于一个测试周期的持续时间，定时信号同相分布，使得它们的边沿将每个测试周期均匀分成 N间隔。每个测试周期名义上开始于T0信号的边沿，并且参考测试事件的每个向量还指示在通过参考定时信号T0到T之一来发生事件的测试周期开始之后的标称时间延迟（N-1）。然而，每当测试仪接收到输入触发信号边沿时，它确定最近的T0信号边沿与触发信号边沿的出现之间的偏移。在随后的测试周期中，测试仪将测试周期的开始和测试事件的发生延迟触发信号边缘偏移的量。在这样做时，测试仪使得针对触发信号边沿的每个后续测试事件的延迟是向量序列的可预测函数。

3. 发明授权

US06330197B1 System for linearizing a programmable delay circuit 有权
标题翻译：用于线性化可编程延迟电路的系统
公开(公告)号：US06330197B1
公开(公告)日：2001-12-11
申请号：US09628702
申请日：2000-07-31
申请人： Jeffrey D. Currin , Jacob Herbold , Manohari Reddy , Mark Dahl , Philip T. Kuglin
发明人： Jeffrey D. Currin , Jacob Herbold , Manohari Reddy , Mark Dahl , Philip T. Kuglin
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , H03L7/0814 , H03L7/0818
摘要： A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay circuit. A linearization system automatically adjusts the value of the control data stored at each of the RAM's N addresses so that the delay provided by the delay circuit is a linear function of the value of the input data. The linearization system provides two periodic reference signals (“beat” and “clock”) wherein the period PB of the beat signal and the period PC of the clock signal are related by the expression PB=PC(N+1)/N. The linearization system iteratively adjusts the control data stored at each RAM address so that when the RAM continuously reads out the control data stored at the Kth RAM address, the Kth edge of the beat signal and every Nth edge thereafter substantially coincides with an edge of the delay circuit output signal.
摘要翻译：具有N个可寻址存储位置的随机存取存储器（RAM）通过指定信号延迟的输入数据来寻址，并且RAM读出控制延迟电路的延迟的控制数据。线性化系统自动调整存储在每个RAM的N个地址中的控制数据的值，使得由延迟电路提供的延迟是输入数据的值的线性函数。线性化系统提供两个周期性参考信号（“拍子”和“时钟”），其中拍频信号的周期PB和时钟信号的周期PC通过表达式PB = PC（N + 1）/ N相关联。线性化系统迭代地调整存储在每个RAM地址处的控制数据，使得当RAM连续地读出存储在第K个RAM地址中的控制数据时，差拍信号的第K个边缘和其后的第N个边缘基本上与延迟电路输出信号。

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