专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07725778B2 Semiconductor integrated circuit and electronic device 有权
标题翻译：半导体集成电路和电子设备
公开(公告)号：US07725778B2
公开(公告)日：2010-05-25
申请号：US12314291
申请日：2008-12-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G11B20/20 , G11C29/00 , G01R31/26
CPC分类号： G11C7/22 , G11C5/04 , G11C7/1045 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , H05K1/0248 , H05K1/0268 , H05K1/14 , H05K2201/044 , H05K2201/09781
摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.
摘要翻译：虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且由测量电路获得的延迟时间用于确定输出电路的信号转换时间。信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。以这种方式，实现了由最近端的反射点减轻反射的信号传输。

82. 发明授权

US07633147B2 Semiconductor unit having two device terminals for every one input/output signal 失效
标题翻译：半导体单元具有用于每一个输入/输出信号的两个器件端子
公开(公告)号：US07633147B2
公开(公告)日：2009-12-15
申请号：US10672551
申请日：2003-09-26
申请人： Seiji Funaba , Hisashi Abo , Takao Ono , Koji Hosokawa , Yoji Nishio , Atsushi Nakamura , Tomohiko Sato
发明人： Seiji Funaba , Hisashi Abo , Takao Ono , Koji Hosokawa , Yoji Nishio , Atsushi Nakamura , Tomohiko Sato
IPC分类号： H01L23/538
CPC分类号： H01L25/105 , H01L23/50 , H01L23/552 , H01L23/60 , H01L23/64 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19032 , H01L2924/19041 , H01L2924/19051 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/112 , H05K1/14 , H05K1/181 , H05K2201/09236 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.
摘要翻译：构成存储器件的半导体单元具有存储芯片，具有三个布线层的封装基板。电源表面（VDD表面）和（GND表面）被布线在封装衬底上，而封装内的DQ总线布线在两个电源表面之间的中间层上。存储器件每一个封装内DQ总线具有两个DQ引脚。封装内的DQ总线通过通孔连接到存储器芯片的信号端子焊盘。鉴于两个DW引脚，用于将封装内DQ DQ总线与信号端子焊盘连接的通孔构成分支线。

83. 再颁专利

USRE40205E1 Semiconductor device and timing control circuit 有权
标题翻译：半导体器件和定时控制电路
公开(公告)号：USRE40205E1
公开(公告)日：2008-04-01
申请号：US10226019
申请日：2002-08-23
申请人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yuichi Okuda , Yoshinobu Nakagome
IPC分类号： G11C11/4076
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals. Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
摘要翻译： <？delete-start id =“DEL-S-00001”date =“20080401”？从可变延迟电路的输出到延迟控制输入的延迟环路的操作速度进行控制。例如，分频电路分别置于可变延迟电路的输入和输出端。通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个输入相位比较器。根据两个信号的相位比较结果执行相位控制。<？delete-end id =“DEL-S-00001”？> <？insert-start id =“INS-S-00001”date = 执行从可变延迟电路的输出到其延迟控制输入的延迟环的操作速度的控制。例如，分频电路分别置于可变延迟电路的输入和输出端。通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个输入相位比较器。根据两个信号的相位之间的比较结果执行相位控制。<？insert-end id =“INS-S-00001”？>

84. 发明申请

US20070255983A1 Semiconductor integrated circuit and electronic device 失效
标题翻译：半导体集成电路和电子设备
公开(公告)号：US20070255983A1
公开(公告)日：2007-11-01
申请号：US11270608
申请日：2005-11-10
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G01R31/28
CPC分类号： G11C7/22 , G11C5/04 , G11C7/1045 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , H05K1/0248 , H05K1/0268 , H05K1/14 , H05K2201/044 , H05K2201/09781
摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.
摘要翻译：虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且通过测量电路获得的延迟时间用于确定输出电路的信号转换时间。信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。以这种方式，实现了由最近端的反射点减轻反射的信号传输。

85. 发明授权

US07051225B2 Memory system, module and register 有权
标题翻译：内存系统，模块和寄存器
公开(公告)号：US07051225B2
公开(公告)日：2006-05-23
申请号：US10427090
申请日：2003-04-30
申请人： Yoji Nishio , Kayoko Shibata , Seiji Funaba
发明人： Yoji Nishio , Kayoko Shibata , Seiji Funaba
IPC分类号： G06F1/04
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1093
摘要： Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replical) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.
摘要翻译：公开了一种存储器命令地址系统和存储器模块，其不仅可以用于266MHzCLK，而且可以用于200MHzCLK，其中PLL，寄存器和DRAM的输入部分中的时钟定时彼此匹配，在寄存器中提供DLL（延迟锁定环），控制来自寄存器的CA信号的输出定时，使得CA信号的建立时间余量和保持时间裕度相对于时钟信号具有额外的等待时间 DRAM = 1.5或2.0彼此相等，使得例如266MHz的时钟操作成为可能。如果使用266MHz和200MHz，通过考虑时序预算，进行控制以延迟输入到触发器的CA信号的定时，该触发器接收提供给触发器的内部时钟信号（intCLK）用于确定来自寄存器的CA信号输出定时。或者，根据所使用的频率，进行控制以在寄存器中提供的副本（复制）和与副本相关联的输出单元之间进行切换，从而简单地通过提供一种模块和一个模块来处理两个频率排序的注册表。

86. 发明申请

US20050099834A1 Stacked memory, memory module and memory system 有权
标题翻译：堆叠内存，内存模块和内存系统
公开(公告)号：US20050099834A1
公开(公告)日：2005-05-12
申请号：US10979157
申请日：2004-11-03
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G06F12/00 , G06F13/16 , G11C5/00 , G11C5/04 , G11C11/401 , H01L25/065 , H01L25/10 , H01L27/10 , H05K1/18 , G11C5/06 , G11C29/00
CPC分类号： H05K1/181 , G11C5/04 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1005 , H01L2225/1023 , H01L2225/107 , H01L2924/13091 , H01L2924/15311 , H01L2924/15321 , H01L2924/3011 , H05K2201/10159 , H05K2201/10515 , H05K2203/1572 , Y02P70/611 , H01L2924/00014 , H01L2924/00
摘要： A point-to-point bus and a daisy chain bus are provided for supplying signals to stacked memories, and the stacked memories are mounted mutually apart by a distance equivalent to the length of the stacked memory on both surfaces of a module substrate. Furthermore, the memory chips arranged in a stacked memory mounted on one surface are set in an active state at the same time alternately with the memory chips arranged in a stacked memory mounted on another surface of the module substrate.
摘要翻译：提供点对点总线和菊花链总线，用于向堆叠的存储器提供信号，堆叠的存储器相互间隔相隔一定距离，与模块基板的两个表面上堆叠的存储器的长度相当。此外，布置在安装在一个表面上的堆叠存储器中的存储器芯片与安装在模块基板的另一表面上的堆叠存储器中布置的存储芯片交替地设置为活动状态。

87. 发明申请

US20050082664A1 Stacked semiconductor device and semiconductor chip control method 审中-公开
标题翻译：堆叠半导体器件和半导体芯片控制方法
公开(公告)号：US20050082664A1
公开(公告)日：2005-04-21
申请号：US10964919
申请日：2004-10-15
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G11C11/408 , G11C5/06 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/413 , H01L23/495 , H01L23/544 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/18 , H01L2223/5444 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06572 , H01L2924/15311 , H01L2924/15331
摘要： Each of stacked memory chips has an ID generator circuit for generating identification information in accordance with its manufacturing process. Since the memory chip manufacturing process implies process variations, the IDs generated by the respective ID generator circuits are different from one another even though the ID generator circuits are identical in design. A memory controller instructs an ID detector circuit to detect the IDs of the respective memory chips, and individually controls the respective memory chips based on the detected IDs.
摘要翻译：每个堆叠的存储器芯片具有ID发生器电路，用于根据其制造过程产生识别信息。由于存储器芯片制造处理意味着处理变化，所以即使ID生成器电路的设计相同，由ID生成器电路生成的ID彼此不同。存储器控制器指示ID检测器电路检测各个存储器芯片的ID，并且基于检测到的ID单独地控制各个存储器芯片。

88. 发明授权

US06657459B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
公开(公告)号：US06657459B2
公开(公告)日：2003-12-02
申请号：US10143762
申请日：2002-05-14
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

89. 发明授权

US06438014B2 High speed access compatible memory module 有权
标题翻译：高速存取兼容内存模块
公开(公告)号：US06438014B2
公开(公告)日：2002-08-20
申请号：US09803148
申请日：2001-03-12
申请人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
发明人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
IPC分类号： G11C506
CPC分类号： G11C5/06 , G11C5/04 , G11C5/063 , H01L23/5387 , H01L25/065 , H01L25/0655 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06579 , H01L2924/01055 , H01L2924/15312 , H01L2924/1532 , H01L2924/3011
摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each of the individual memory modules are connected in serial form, and each of the individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.
摘要翻译：模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对，以及分别连接在多个模块数据端子对之间的多个模块数据布线。多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据配线不构成相对于数据的分支布线总线在内存系统的主板上。在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。

90. 发明授权

US06387028B1 Packaging machine 失效
标题翻译：包装机
公开(公告)号：US06387028B1
公开(公告)日：2002-05-14
申请号：US09536989
申请日：2000-03-29
申请人： Yoji Nishio , Kazumasa Nishiuchi , Michio Ueda
发明人： Yoji Nishio , Kazumasa Nishiuchi , Michio Ueda
IPC分类号： B31B128
CPC分类号： B65B3/025 , B31B50/64 , B65B43/24
摘要： A packaging machine comprises a movable body having mandrels and intermittently drivable so as to stop each of the mandrels at a process station while carrying containers as fitted around the respective mandrels with a bottom forming portion of each container projecting outward from the mandrel, and a bottom breaker for forming folds in a bottom forming end portion of the container fitted around the mandrel as halted at the process station so as to render the end portion foldable flat. The bottom breaker has first folding means for initially folding the second and fourth bottom panels in two into triangles, and second folding means for subsequently folding first and third bottom panels. The second folding means has an upstream arm movable into pressing contact with the first bottom panel, and a downstream arm movable into pressing contact with the third bottom panel. The downstream arm is provided with a pressure plate at a portion thereof to be contacted with the third bottom panel.
摘要翻译：包装机包括具有心轴并间歇地驱动的可移动体，以便在处理站处停止每个心轴，同时将容器装配在相应的心轴周围，每个容器的底部形成部分从心轴向外突出，底部用于在装配在心轴上的容器的底部形成端部中形成折叠的断路器，在处理站处停止，以使端部可折叠平坦。底部破碎器具有用于将第二和第四底板初始折叠成两个成三角形的第一折叠装置，以及用于随后折叠第一和第三底板的第二折叠装置。第二折叠装置具有可移动成与第一底板按压接触的上游臂，以及可移动地与第三底板压接的下游臂。下游臂在其一部分处设置有压板，以与第三底板接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式