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81. 发明授权

US08106454B2 Power semiconductor device and method for manufacturing same 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08106454B2
公开(公告)日：2012-01-31
申请号：US12266331
申请日：2008-11-06
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/00
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66734 , H01L29/7813
摘要： A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant.
摘要翻译：垂直功率半导体器件包括形成在电池部分和终端部分中的第一导电类型的第一半导体层，围绕电池部分的端接部分，形成在第一半导体层上的第二导电类型的第二半导体层单元部分，部分地形成在第二半导体层上的第一导电类型的第三半导体层和形成在终端部分中的第一半导体层上的第二导电类型的保护环层。保护环层中的净杂质浓度一般是倾斜的，在其下侧相对较高，而在其上侧相对较低。或者，保护环层中的净杂质浓度恒定。

82. 发明授权

US07927952B2 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07927952B2
公开(公告)日：2011-04-19
申请号：US12128326
申请日：2008-05-28
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L21/336
CPC分类号： H01L29/0619 , H01L29/0615 , H01L29/1095 , H01L29/66734
摘要： A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type.
摘要翻译：制造半导体器件的方法包括在第一导电类型的衬底上形成第一导电类型的半导体层; 在第一导电类型的半导体层的表面上形成抗氧化层，所述抗氧化层仅通过用于形成所述第二导电类型的保护环层的区域具有孔; 通过将离子注入形成所述抗氧化层的表面，在第一导电类型的半导体层的表面中形成第二导电类型的保护环层; 至少在所述孔中形成氧化物层; 在第一导电类型的半导体层的表面中形成与第二导电类型的保护环层相邻的第二导电类型的基极层; 以及通过将离子注入第二导电类型的基极层而形成第一导电类型的扩散层。

83. 发明申请

US20100096696A1 SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR FOR USE AS A HIGH-SPEED SWITCHING DEVICE AND A POWER DEVICE 有权
标题翻译：包括用作高速开关器件和功率器件的场效应晶体管的半导体器件
公开(公告)号：US20100096696A1
公开(公告)日：2010-04-22
申请号：US12645072
申请日：2009-12-22
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

84. 发明授权

US07692242B2 Semiconductor device used as high-speed switching device and power device 失效
标题翻译：半导体器件用作高速开关器件和功率器件
公开(公告)号：US07692242B2
公开(公告)日：2010-04-06
申请号：US11505337
申请日：2006-08-17
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L29/04 , H01L29/06
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

85. 发明申请

US20080299725A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080299725A1
公开(公告)日：2008-12-04
申请号：US12128326
申请日：2008-05-28
申请人： Miwako AKIYAMA , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako AKIYAMA , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L21/336
CPC分类号： H01L29/0619 , H01L29/0615 , H01L29/1095 , H01L29/66734
摘要： A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type.
摘要翻译：制造半导体器件的方法包括在第一导电类型的衬底上形成第一导电类型的半导体层; 在第一导电类型的半导体层的表面上形成抗氧化层，所述抗氧化层仅通过用于形成所述第二导电类型的保护环层的区域具有孔; 通过将离子注入形成所述抗氧化层的表面，在第一导电类型的半导体层的表面中形成第二导电类型的保护环层; 至少在所述孔中形成氧化物层; 在第一导电类型的半导体层的表面中形成与第二导电类型的保护环层相邻的第二导电类型的基极层; 以及通过将离子注入第二导电类型的基极层而形成第一导电类型的扩散层。

86. 发明申请

US20060231894A1 Transistor 失效
公开(公告)号：US20060231894A1
公开(公告)日：2006-10-19
申请号：US11405672
申请日：2006-04-18
申请人： Mitsuhiko Kitagawa , Takashi Nishimura , Yusuke Kawaguchi , Syotaro Ono
发明人： Mitsuhiko Kitagawa , Takashi Nishimura , Yusuke Kawaguchi , Syotaro Ono
IPC分类号： H01L27/12
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/4933 , H01L29/7397 , H01L29/7824 , H01L29/7831 , H01L29/78603 , H01L29/78624
摘要： A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions of a second conductivity type, the source regions being alternated with the base contact regions, a drain portion of the first conductivity type, and a base region of the second conductivity type provided between the source portion and the drain portion, the base region being in contact with the source regions and the base contact regions. A junction between the source regions and the base region is closer to the drain portion side than a junction between the base contact regions and the base region.

87. 发明授权

US09105716B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09105716B2
公开(公告)日：2015-08-11
申请号：US12944632
申请日：2010-11-11
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L21/336 , H01L29/78 , H01L29/06 , H01L29/10 , H01L29/66 , H01L21/265 , H01L29/08 , H01L29/417
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0869 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.
摘要翻译：半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层设置在第一半导体层的主表面上并且具有比第一半导体层的杂质浓度低的第二半导体层; 设置在第二半导体层上的第二导电类型的第三半导体层; 选择性地设置在第三半导体层上的第一导电类型的第四半导体层; 设置在穿过所述第三半导体层并到达所述第二半导体层的沟槽中的栅电极; 与所述第四半导体层接触的第一主电极，并且通过设置成在所述连续的栅电极之间穿过所述第四半导体层的接触槽使所述第三半导体层接触; 设置在与所述第一半导体层的主表面相反的表面上的第二主电极; 以及第二导电类型的第五半导体层，设置在与所述接触槽下方的部分对应的所述第二半导体层的内部。第五半导体层的最上部与第三半导体层接触，第五半导体层的最下部分的杂质浓度比第五半导体层中的其他部分杂质浓度高，位于第二半导体层中，第一半导体层，第五半导体层从最上部到最下部较窄。

88. 发明授权

US08008715B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08008715B2
公开(公告)日：2011-08-30
申请号：US12185630
申请日：2008-08-04
申请人： Yusuke Kawaguchi , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
发明人： Yusuke Kawaguchi , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/7811
摘要： There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.
摘要翻译：提供一种半导体器件，包括：第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极，与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层，并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极，其间插入有栅极绝缘膜; 以及栅极引线部分，其设置在栅极布线下方的沟槽内部，栅极绝缘膜介于其间并与栅极布线和栅电极接触。

89. 发明授权

US07910984B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07910984B2
公开(公告)日：2011-03-22
申请号：US12355591
申请日：2009-01-16
申请人： Yoshihiro Yamaguchi , Yusuke Kawaguchi , Miwako Akiyama
发明人： Yoshihiro Yamaguchi , Yusuke Kawaguchi , Miwako Akiyama
IPC分类号： H01L29/76
CPC分类号： H01L27/088 , H01L21/823487 , H01L23/481 , H01L23/482 , H01L27/0629 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/4175 , H01L29/41766 , H01L29/4238 , H01L29/7813 , H01L29/7825 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode.
摘要翻译：半导体器件包括：半导体衬底; 形成在所述半导体衬底的第一区域的上部的横向MOSFET; 形成在所述半导体衬底的第二区域中的垂直MOSFET; 背面电极，其形成在所述半导体衬底的下表面上并且连接到所述垂直MOSFET的源极/漏极区域的下部区域; 以及穿透半导体衬底并将横向MOSFET的源极/漏极区域中的一个连接到背面电极的连接构件。

90. 发明申请

US20100159659A1 SEMICONDUCTOR DEVICE USED AS HIGH-SPEED SWITCHING DEVICE AND POWER DEVICE 有权
标题翻译：用作高速切换装置和电源装置的半导体装置
公开(公告)号：US20100159659A1
公开(公告)日：2010-06-24
申请号：US12716352
申请日：2010-03-03
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L21/336
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

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