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81. 发明申请

US20130320397A1 Fully Isolated LIGBT and Methods for Forming the Same 有权
公开(公告)号：US20130320397A1
公开(公告)日：2013-12-05
申请号：US13601229
申请日：2012-08-31
申请人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： H01L29/739 , H01L21/332
CPC分类号： H01L29/66325 , H01L21/265 , H01L21/304 , H01L21/76 , H01L21/761 , H01L21/76224 , H01L29/0696 , H01L29/7393 , H01L29/7394
摘要： A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.

82. 发明授权

US08546860B2 Stress engineering to reduce dark current of CMOS image sensors 有权
标题翻译：应力工程可以减少CMOS图像传感器的暗电流
公开(公告)号：US08546860B2
公开(公告)日：2013-10-01
申请号：US13494769
申请日：2012-06-12
申请人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
发明人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
IPC分类号： H01L31/113 , H01L31/173
CPC分类号： H01L27/1463 , H01L21/324 , H01L21/823878 , H01L22/34 , H01L27/14689 , H01L29/7842
摘要： This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.
摘要翻译：本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色细胞计数由第一次压力引起。

83. 发明授权

US08383440B2 Light shield for CMOS imager 有权
标题翻译： CMOS成像器的屏蔽
公开(公告)号：US08383440B2
公开(公告)日：2013-02-26
申请号：US13081120
申请日：2011-04-06
申请人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
发明人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
IPC分类号： H01L21/00
CPC分类号： H01L27/14654 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.
摘要翻译：提供了一种用于为CMOS成像器提供遮光罩的系统和方法。光屏蔽包括形成在感光元件和相邻电路之间的点之上的结构。该结构由光敏元件上的电介质层中形成的诸如金属，金属合金，金属化合物等的遮光材料形成。

84. 发明授权

US08148223B2 1T MIM memory for embedded ram application in soc 有权
标题翻译： 1T MIM存储器，用于嵌入式RAM应用
公开(公告)号：US08148223B2
公开(公告)日：2012-04-03
申请号：US11437673
申请日：2006-05-22
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

85. 发明申请

US20090321888A1 ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR 有权
标题翻译：背面照明传感器对准
公开(公告)号：US20090321888A1
公开(公告)日：2009-12-31
申请号：US12553586
申请日：2009-09-03
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

86. 发明申请

US20090243025A1 PIXEL STRUCTURE WITH A PHOTODETECTOR HAVING AN EXTENDED DEPLETION DEPTH 审中-公开
标题翻译：具有延伸深度深度的光电转换器的像素结构
公开(公告)号：US20090243025A1
公开(公告)日：2009-10-01
申请号：US12054505
申请日：2008-03-25
申请人： Eric G. Stevens , Hung Q. Doan , Shou-Gwo Wuu , Chung-Wei Chang
发明人： Eric G. Stevens , Hung Q. Doan , Shou-Gwo Wuu , Chung-Wei Chang
IPC分类号： H01L31/101
CPC分类号： H01L27/14609 , H01L27/14603 , H01L27/14689
摘要： An image sensor includes an imaging area that includes a plurality of pixels that are formed in a substrate layer of a first conductivity type. Each pixel includes a collection region that is formed in a portion of the substrate layer and doped with a dopant of a first conductivity type. A plurality of wells are disposed in portions of the substrate layer and doped with another dopant of the second conductivity type. Each well is positioned laterally adjacent to each collection region. A buried layer spans the imaging area and is disposed in a portion of the substrate layer that is beneath the photodetectors and the wells. The buried layer is doped with a dopant of a second conductivity type. Each collection region, each well, and the buried layer are formed such that a region of the substrate layer having substantially the same doping as the substrate layer resides between each collection region and the buried layer.
摘要翻译：图像传感器包括具有形成在第一导电类型的衬底层中的多个像素的成像区域。每个像素包括形成在衬底层的一部分中并掺杂有第一导电类型的掺杂剂的收集区域。多个阱设置在衬底层的部分中并且掺杂有另一种第二导电类型的掺杂剂。每个井横向定位在每个收集区域附近。掩埋层跨越成像区域并且被布置在基底层的位于光电检测器和孔下方的部分中。掩埋层掺杂有第二导电类型的掺杂剂。每个收集区域，每个阱和掩埋层被形成为使得具有与衬底层基本相同的掺杂的衬底层的区域驻留在每个收集区域和掩埋层之间。

87. 发明授权

US07485940B2 Guard ring structure for improving crosstalk of backside illuminated image sensor 有权
标题翻译：保护环结构，用于改善背面照明图像传感器的串扰
公开(公告)号：US07485940B2
公开(公告)日：2009-02-03
申请号：US11626757
申请日：2007-01-24
申请人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Dun-Nian Yaung
发明人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Dun-Nian Yaung
IPC分类号： H01L31/00 , H01L23/28
CPC分类号： H01L27/1463 , H01L27/1464 , H01L27/14683
摘要： The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive light directed towards the back surface; and a sensor isolation feature formed in the substrate, and disposed horizontally between two adjacent elements of the plurality of sensor elements, and vertically between the back surface and the front surface.
摘要翻译：本公开提供了背面照明半导体器件。该装置包括具有前表面和后表面的基板; 形成在所述基板中的多个传感器元件，所述多个传感器元件中的每一个被设计和配置成接收朝向所述后表面的光; 以及形成在所述基板中的传感器隔离特征，并且水平地设置在所述多个传感器元件的两个相邻元件之间，并且在所述后表面和所述前表面之间垂直。

88. 发明申请

US20080217719A1 Method For Reducing Crosstalk In Image Sensors Using Implant Technology 有权
标题翻译：使用植入技术降低图像传感器串扰的方法
公开(公告)号：US20080217719A1
公开(公告)日：2008-09-11
申请号：US11682633
申请日：2007-03-06
申请人： J. C. Liu , C. H. Cheng , Chien-Hsien Tseng , Alex Hsu , Feng-Jia Shiu , Shou-Gwo Wuu
发明人： J. C. Liu , C. H. Cheng , Chien-Hsien Tseng , Alex Hsu , Feng-Jia Shiu , Shou-Gwo Wuu
IPC分类号： H01L31/00 , H01L21/76
CPC分类号： H01L27/1463 , H01L27/14689
摘要： The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.
摘要翻译：本公开提供了一种图像传感器半导体器件。提供具有第一类电导率的半导体衬底。在半导体衬底中形成多个传感器元件。在多个传感器元件之间形成隔离特征。执行离子注入工艺以使用至少两种不同的注入能量形成具有基本上位于隔离特征下的第一类型导电的掺杂区域。

89. 发明授权

US07423306B2 CMOS image sensor devices 有权
标题翻译： CMOS图像传感器设备
公开(公告)号：US07423306B2
公开(公告)日：2008-09-09
申请号：US11527464
申请日：2006-09-27
申请人： J. C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： J. C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L21/00
CPC分类号： H01L27/1463 , H01L27/14609 , H01L27/14627 , H01L27/14632 , H01L27/14645
摘要： A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel region over the substrate. A second well region is formed in a potion of the first well region of the pixel region, having a second conductivity type opposite to the first conductivity type. A top surface region is formed in a top portion of the second well region, having the first conductivity type. A MOS transistor formed on portions the pixel region, having a pair of source/drain regions formed in the first well region, wherein the source/drain regions are formed of the second conductivity type and one thereof electrically connects the first and well doping regions and the first well region is formed with a depth greater than that of the adjacent STI structure.
摘要翻译：像素包括基板，该基板包括形成在基板顶部的第一阱区域，具有第一导电类型。在衬底的第一阱区域中形成多个浅沟槽隔离（STI）结构，在衬底上限定像素区域。第二阱区形成在像素区的第一阱区的一个部分中，具有与第一导电类型相反的第二导电类型。顶表面区域形成在具有第一导电类型的第二阱区域的顶部。形成在像素区域的部分上的MOS晶体管，其具有形成在第一阱区域中的一对源极/漏极区域，其中源极/漏极区域由第二导电类型形成，并且其中一个电连接第一和阱掺杂区域，第一阱区域的深度大于相邻STI结构的深度。

90. 发明申请

US20080111169A1 CMOS image sensor devices 有权
公开(公告)号：US20080111169A1
公开(公告)日：2008-05-15
申请号：US11527464
申请日：2006-09-27
申请人： J.C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： J.C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L27/146
CPC分类号： H01L27/1463 , H01L27/14609 , H01L27/14627 , H01L27/14632 , H01L27/14645
摘要： A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel region over the substrate. A second well region is formed in a potion of the first well region of the pixel region, having a second conductivity type opposite to the first conductivity type. A top surface region is formed in a top portion of the second well region, having the first conductivity type. A MOS transistor formed on portions the pixel region, having a pair of source/drain regions formed in the first well region, wherein the source/drain regions are formed of the second conductivity type and one thereof electrically connects the first and well doping regions and the first well region is formed with a depth greater than that of the adjacent STI structure.

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