专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08546860B2 Stress engineering to reduce dark current of CMOS image sensors 有权
标题翻译：应力工程可以减少CMOS图像传感器的暗电流
公开(公告)号：US08546860B2
公开(公告)日：2013-10-01
申请号：US13494769
申请日：2012-06-12
申请人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
发明人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
IPC分类号： H01L31/113 , H01L31/173
CPC分类号： H01L27/1463 , H01L21/324 , H01L21/823878 , H01L22/34 , H01L27/14689 , H01L29/7842
摘要： This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.
摘要翻译：本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色细胞计数由第一次压力引起。

2. 发明授权

US08216905B2 Stress engineering to reduce dark current of CMOS image sensors 有权
标题翻译：应力工程可以减少CMOS图像传感器的暗电流
公开(公告)号：US08216905B2
公开(公告)日：2012-07-10
申请号：US12768063
申请日：2010-04-27
申请人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
发明人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
IPC分类号： H01L21/336
CPC分类号： H01L27/1463 , H01L21/324 , H01L21/823878 , H01L22/34 , H01L27/14689 , H01L29/7842
摘要： The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.
摘要翻译：上述有源像素单元结构和制备这种结构的方法能够减少有源像素单元的暗电流和白细胞计数。制备有源像素单元结构的过程在衬底上引入应力，这可能导致有源像素单元的暗电流和白细胞计数增加。通过沉积应力层作为预金属介电层的一部分，其应力引起应力，暗电流和白细胞计数都可以减小。如果有源像素单元的晶体管是NMOS，则载流子迁移率也可以通过拉伸应力层增加。拉曼光谱可用于测量在沉积应力层之前施加在基底上的应力。

3. 发明授权

US08778717B2 Local oxidation of silicon processes with reduced lateral oxidation 有权
标题翻译：硅工艺的局部氧化减少了横向氧化
公开(公告)号：US08778717B2
公开(公告)日：2014-07-15
申请号：US12726215
申请日：2010-03-17
申请人： Ru-Shang Hsiao , Chung-Te Lin , Nai-Wen Cheng , Yin-Kai Liao , Wei Chuang Wu
发明人： Ru-Shang Hsiao , Chung-Te Lin , Nai-Wen Cheng , Yin-Kai Liao , Wei Chuang Wu
IPC分类号： H01L21/00
CPC分类号： H01L21/76213 , H01L21/26513 , H01L21/26533 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.
摘要翻译：形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入硅衬底中以形成p型区域。在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。

4. 发明申请

US20110230002A1 Local Oxidation of Silicon Processes with Reduced Lateral Oxidation 有权
标题翻译：具有减少横向氧化的硅工艺的局部氧化
公开(公告)号：US20110230002A1
公开(公告)日：2011-09-22
申请号：US12726215
申请日：2010-03-17
申请人： Ru-Shang Hsiao , Chung-Te Lin , Nai-Wen Cheng , Yin-Kai Liao , Wei Chuang Wu
发明人： Ru-Shang Hsiao , Chung-Te Lin , Nai-Wen Cheng , Yin-Kai Liao , Wei Chuang Wu
IPC分类号： H01L21/26
CPC分类号： H01L21/76213 , H01L21/26513 , H01L21/26533 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.
摘要翻译：形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入到硅衬底中以形成p型区域。在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。

5. 发明授权

US08158474B2 Semiconductor device with localized stressor 有权
标题翻译：具有局部应激源的半导体器件
公开(公告)号：US08158474B2
公开(公告)日：2012-04-17
申请号：US12873889
申请日：2010-09-01
申请人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
发明人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
IPC分类号： H01L21/0243 , H01L23/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.
摘要翻译：提供具有局部应力源的诸如PMOS晶体管的半导体器件。凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。这些凹部填充有应力诱导层。去除虚拟凹槽并形成轻掺杂的排水沟。此后，形成新的间隔物并且应力诱导层凹陷。可以执行一个或多个附加植入物以完成源极/漏极区域。在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

6. 发明授权

US07825477B2 Semiconductor device with localized stressor 有权
标题翻译：具有局部应激源的半导体器件
公开(公告)号：US07825477B2
公开(公告)日：2010-11-02
申请号：US11738968
申请日：2007-04-23
申请人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
发明人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
IPC分类号： H01L23/62 , H01L29/78 , H01L21/0234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.
摘要翻译：提供具有局部应力源的诸如PMOS晶体管的半导体器件。凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。这些凹部填充有应力诱导层。去除虚拟凹槽并形成轻掺杂的排水沟。此后，形成新的间隔物并且应力诱导层凹陷。可以执行一个或多个附加植入物以完成源极/漏极区域。在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

7. 发明申请

US20100330755A1 Semiconductor Device With Localized Stressor 有权
标题翻译：具有局部应力的半导体器件
公开(公告)号：US20100330755A1
公开(公告)日：2010-12-30
申请号：US12873889
申请日：2010-09-01
申请人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
发明人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.
摘要翻译：提供具有局部应力源的诸如PMOS晶体管的半导体器件。凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。这些凹部填充有应力诱导层。去除虚拟凹槽并形成轻掺杂的排水沟。此后，形成新的间隔物并且应力诱导层凹陷。可以执行一个或多个附加植入物以完成源极/漏极区域。在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

8. 发明申请

US20080258233A1 Semiconductor Device with Localized Stressor 有权
标题翻译：具有局部应力的半导体器件
公开(公告)号：US20080258233A1
公开(公告)日：2008-10-23
申请号：US11738968
申请日：2007-04-23
申请人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
发明人： Ru-Shang Hsiao , Min Cao , Chung-Te Lin , Ta-Ming Kuan , Cheng-Tung Hsu
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.
摘要翻译：提供具有局部应力源的诸如PMOS晶体管的半导体器件。凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。这些凹部填充有应力诱导层。去除虚拟凹槽并形成轻掺杂的排水沟。此后，形成新的间隔物并且应力诱导层凹陷。可以执行一个或多个附加植入物以完成源极/漏极区域。在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

9. 发明授权

US08051392B2 Performance-aware logic operations for generating masks 有权
公开(公告)号：US08051392B2
公开(公告)日：2011-11-01
申请号：US12212088
申请日：2008-09-17
申请人： Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
发明人： Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
IPC分类号： G06F17/50 , G06F7/66 , G06K9/00 , H01L21/66
摘要： A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

10. 发明申请

US20080272410A1 Self-Aligned Spacer Contact 审中-公开
标题翻译：自对准垫片联系人
公开(公告)号：US20080272410A1
公开(公告)日：2008-11-06
申请号：US11743519
申请日：2007-05-02
申请人： Chung-Te Lin
发明人： Chung-Te Lin
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76831 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) having self-aligned spacer contacts is provided. In accordance with embodiments of the present invention, a transistor, having a gate electrode and source/drain regions formed on opposing sides of the gate electrode, is covered with a first dielectric layer. A first contact opening is formed in the first dielectric layer to expose at least a portion of one of the source/drain regions. A second dielectric layer is formed over the first dielectric layer. Thereafter, an inter-layer dielectric layer is formed over the second dielectric layer and a second contact opening is formed through the inter-layer dielectric layer. In an embodiment, an etch-back process may be performed on the second dielectric layer prior to forming the inter-layer dielectric layer.
摘要翻译：提供了具有自对准间隔触点的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，具有形成在栅电极的相对侧上的栅电极和源极/漏极区的晶体管被第一介电层覆盖。在第一电介质层中形成第一接触开口以暴露源/漏区之一的至少一部分。在第一电介质层上形成第二电介质层。此后，在第二电介质层上形成层间电介质层，通过层间电介质层形成第二接触开口。在一个实施例中，可以在形成层间电介质层之前在第二电介质层上执行回蚀工艺。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式