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81. 发明授权

US08426960B2 Wafer level chip scale packaging 有权
标题翻译：晶圆级芯片级封装
公开(公告)号：US08426960B2
公开(公告)日：2013-04-23
申请号：US11963690
申请日：2007-12-21
申请人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
发明人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
IPC分类号： H01L23/48
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/02 , H01L24/11 , H01L24/17 , H01L2221/68354 , H01L2224/0231 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
摘要翻译：公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。将包含多个半导体芯片的晶片安装在封装基板上。多个半导体芯片包括暴露背面的一个或多个电极。去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。将导电材料施加到半导体芯片的背面和间隙中。然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。

82. 发明授权

US08067822B2 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US08067822B2
公开(公告)日：2011-11-29
申请号：US12215049
申请日：2008-06-23
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/52 , H01L23/485 , H01L23/495
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

83. 发明申请

US20110241214A1 Virtually Substrate-less Composite Power Semiconductor Device and Method 有权
标题翻译：几何无基板复合功率半导体器件及方法
公开(公告)号：US20110241214A1
公开(公告)日：2011-10-06
申请号：US12749696
申请日：2010-03-30
申请人： Tao Feng , Yueh-Se Ho
发明人： Tao Feng , Yueh-Se Ho
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/561 , H01L23/142 , H01L23/3114 , H01L23/49827 , H01L24/29 , H01L24/92 , H01L2224/29101 , H01L2224/2919 , H01L2224/8385 , H01L2224/9202 , H01L2224/94 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.
摘要翻译：公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

84. 发明申请

US20090321929A1 Standing chip scale package 有权
标题翻译：常规芯片级封装
公开(公告)号：US20090321929A1
公开(公告)日：2009-12-31
申请号：US12217136
申请日：2008-06-30
申请人： Tao Feng , Anup Bhalla , Yueh-Se Ho
发明人： Tao Feng , Anup Bhalla , Yueh-Se Ho
IPC分类号： H01L21/60 , H01L23/498
CPC分类号： H01L24/16 , H01L2224/05568 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/13099 , H01L2224/16 , H01L2224/32145 , H01L2224/73253 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/15153 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00014
摘要： A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.
摘要翻译：公开了一种立式芯片级封装。立式芯片级封装提供与芯片两侧的凸起器件触点的电连接。该封装可以以直立形式与印刷电路板耦合，使得凸起芯片的前侧和后侧基本上垂直于安装表面。还公开了制造立式芯片级封装的工艺。

85. 发明授权

US07211877B1 Chip scale surface mount package for semiconductor device and process of fabricating the same 有权
标题翻译：用于半导体器件的芯片级表面贴装封装及其制造方法
公开(公告)号：US07211877B1
公开(公告)日：2007-05-01
申请号：US11082080
申请日：2005-03-15
申请人： Felix Zandman , Y. Mohammed Kasem , Yueh-Se Ho
发明人： Felix Zandman , Y. Mohammed Kasem , Yueh-Se Ho
IPC分类号： H01L23/544 , H01L21/331
CPC分类号： H01L21/6835 , H01L21/6836 , H01L23/492 , H01L23/49805 , H01L23/49816 , H01L24/11 , H01L24/24 , H01L24/27 , H01L24/81 , H01L24/82 , H01L24/97 , H01L2221/68327 , H01L2221/68377 , H01L2224/1132 , H01L2224/13099 , H01L2224/24226 , H01L2224/274 , H01L2224/76155 , H01L2224/8121 , H01L2224/81815 , H01L2224/82102 , H01L2224/83191 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2224/82 , H01L2924/00
摘要： A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.
摘要翻译：在晶片尺寸上制造在骰子的两侧形成触点的半导体封装。晶片的背面附着在金属板上。分割骰子的划痕线被锯切以露出金属板，但切口不延伸穿过金属板。可以包括多个子层的金属层形成在骰子的前侧，金属覆盖金属板的暴露部分并延伸骰子的侧边缘。金属层的分开的部分也可以覆盖骰子正面上的连接垫。使用与用于制造第一组锯切的刀片相比较窄的第二组锯切与第一组锯切重合。结果，金属层保留在连接骰子（通过金属板）的前侧和前侧的骰子的侧边缘上。由于不需要引线键合，所以产生的封装是坚固的，并且在芯片的背面和前面之间提供低电阻电连接。

86. 发明申请

US20050280133A1 Multiple device package 审中-公开
标题翻译：多器件封装
公开(公告)号：US20050280133A1
公开(公告)日：2005-12-22
申请号：US10873743
申请日：2004-06-21
申请人： Leeshawn Luo , Anup Bhalla , Sik Lui , Yueh-Se Ho , Mike Chang , Xiao Zhang
发明人： Leeshawn Luo , Anup Bhalla , Sik Lui , Yueh-Se Ho , Mike Chang , Xiao Zhang
IPC分类号： H01L21/48 , H01L23/495
CPC分类号： H01L23/49562 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/484 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/49111 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package and method of assembling a semiconductor package is disclosed. The semiconductor package includes a first device mounted on a leadframe and a second device mounted on the leadframe. The leadframe has leads extending to the exterior of the package. An anvil may be used to mount a device on the package. The anvil may include two side portions to support the leads of the package, two end portions connected to the two side portions, and a cutout region.
摘要翻译：公开了一种组装半导体封装的半导体封装和方法。半导体封装包括安装在引线框架上的第一器件和安装在引线框架上的第二器件。引线框架具有延伸到封装外部的引线。可以使用砧座将装置安装在包装上。砧座可以包括用于支撑包装的引线的两个侧部，连接到两个侧部的两个端部和切口区域。

87. 发明申请

US20050145996A1 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US20050145996A1
公开(公告)日：2005-07-07
申请号：US10972746
申请日：2004-10-25
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik Lui , Mike Chang
IPC分类号： H01L21/60 , H01L23/485 , H01L23/495 , H01L23/50 , H01L23/34
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种具有引线框架（108）的半导体集成电路封装，该引线框架（108）包括设置在管芯（100）下方的引线框焊盘（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和管芯（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。该集成电路适用于MOSFET器件，并且焊接金属区域（101a）用于源极端子（101）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

88. 发明授权

US06841852B2 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US06841852B2
公开(公告)日：2005-01-11
申请号：US10189333
申请日：2002-07-02
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L21/60 , H01L23/485 , H01L23/495 , H01L23/50 , H01L23/48
CPC分类号： H01L24/85 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05552 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

89. 发明授权

US5904525A Fabrication of high-density trench DMOS using sidewall spacers 失效
标题翻译：使用侧壁间隔件制造高密度沟槽DMOS
公开(公告)号：US5904525A
公开(公告)日：1999-05-18
申请号：US646593
申请日：1996-05-08
申请人： Fwu-Iuan Hshieh , Yueh-Se Ho , Bosco Lan , Jowei Dun
发明人： Fwu-Iuan Hshieh , Yueh-Se Ho , Bosco Lan , Jowei Dun
IPC分类号： H01L21/26 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/404 , H01L29/0696 , Y10S148/126
摘要： A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers. The peripheries of the diffusion-inhibiting regions covered by the remaining portions of the first and second oxide layers inhibit lateral diffusion of the deep body diffusions without significantly inhibiting diffusion depth.
摘要翻译：一种用于形成具有在半导体衬底上形成的外延层上占据最小面积的深体区的沟槽DMOS晶体管的方法。第一氧化物层形成在外延层上并且被图案化以限定将在其下形成深体区域的深体区域。接下来，在形成覆盖深体区域的第二氧化物层和第一氧化物层的剩余部分之前，在每个深体区域中形成第一导电类型的扩散抑制区域。然后去除第二氧化物层的部分以暴露扩散抑制区域的中心，从第二氧化物层留下第一氧化物层和氧化物侧壁间隔物以覆盖扩散抑制区域的周边。然后执行第二导电类型的深体扩散，导致在侧壁间隔件之间的外延层中形成深体区。由第一和第二氧化物层的剩余部分覆盖的扩散抑制区域的周边阻止深体扩散的横向扩散，而不显着抑制扩散深度。

90. 发明授权

US5767578A Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation 失效
标题翻译：表面贴装和倒装芯片技术，具有金刚石膜钝化功能，可完全集成电路隔离
公开(公告)号：US5767578A
公开(公告)日：1998-06-16
申请号：US634957
申请日：1996-04-19
申请人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun , Hans-Jurgen Fusser , Reinhard Zachai
发明人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun , Hans-Jurgen Fusser , Reinhard Zachai
IPC分类号： H01L23/29 , H01L23/367 , H01L23/373 , H01L23/34
CPC分类号： H01L23/3672 , H01L23/29 , H01L23/3732 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/14
摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.
摘要翻译：集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。最初，芯片基板具有常规的厚度并且在其中形成半导体器件。在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。钝化层是提供电绝缘和导热性的CVD金刚石膜。去除衬底背面（通过研磨和/或CMP）以暴露沟槽的底部。这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。此后，漏极或集电极电触点设置在基板背面上。在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。然后将晶片以两种版本刻成模具，而不需要进一步的包装。

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