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81. 发明授权

US07485918B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07485918B2
公开(公告)日：2009-02-03
申请号：US11797670
申请日：2007-05-07
申请人： Akihito Yamamoto , Yoshio Ozawa
发明人： Akihito Yamamoto , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device including a gate dielectric film provided on at least one site on a surface of a semiconductor substrate, at least one first gate electrode provided on the gate dielectric film, an inter-electrode dielectric film provided while covering a surface of the first gate electrode, at least partial film thickness of a portion covering a portion other than a corner portion that does not come into contact with the gate dielectric film from among a plurality of corner portions of the first gate electrode being formed to be smaller than at least partial film thickness of a portion covering the corner portion that does not come into contact with the gate dielectric film, and a second gate electrode provided while covering a surface of the inter-electrode dielectric film.
摘要翻译：一种半导体器件，包括设置在半导体衬底的表面上的至少一个位置处的栅极电介质膜，设置在栅极电介质膜上的至少一个第一栅电极，设置在覆盖第一栅极的表面的电极间电介质膜所述第一栅电极的多个角部中的与所述栅电介质膜不接触的角部以外的部分的至少部分膜厚成形为小于至少部分覆盖与栅极电介质膜不接触的角部的部分的膜厚度以及覆盖电极间电介质膜的表面的第二栅电极。

82. 发明申请

US20110272745A1 SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20110272745A1
公开(公告)日：2011-11-10
申请号：US13185930
申请日：2011-07-19
申请人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
发明人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L27/105
CPC分类号： H01L27/249 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L29/513 , H01L29/518 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
摘要翻译：半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

83. 发明申请

US20110108905A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110108905A1
公开(公告)日：2011-05-12
申请号：US13007258
申请日：2011-01-14
申请人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

84. 发明申请

US20080012061A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080012061A1
公开(公告)日：2008-01-17
申请号：US11687758
申请日：2007-03-19
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮置栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

85. 发明申请

US20120181598A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20120181598A1
公开(公告)日：2012-07-19
申请号：US13430153
申请日：2012-03-26
申请人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

86. 发明授权

US07982259B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07982259B2
公开(公告)日：2011-07-19
申请号：US11687758
申请日：2007-03-19
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

87. 发明申请

US20070262372A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070262372A1
公开(公告)日：2007-11-15
申请号：US11797670
申请日：2007-05-07
申请人： Akihito Yamamoto , Yoshio Ozawa
发明人： Akihito Yamamoto , Yoshio Ozawa
IPC分类号： H01L29/792
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device including a gate dielectric film provided on at least one site on a surface of a semiconductor substrate, at least one first gate electrode provided on the gate dielectric film, an inter-electrode dielectric film provided while covering a surface of the first gate electrode, at least partial film thickness of a portion covering a portion other than a corner portion that does not come into contact with the gate dielectric film from among a plurality of corner portions of the first gate electrode being formed to be smaller than at least partial film thickness of a portion covering the corner portion that does not come into contact with the gate dielectric film, and a second gate electrode provided while covering a surface of the inter-electrode dielectric film.
摘要翻译：一种半导体器件，包括设置在半导体衬底的表面上的至少一个位置处的栅极电介质膜，设置在栅极电介质膜上的至少一个第一栅电极，设置在覆盖第一栅极的表面的电极间电介质膜所述第一栅电极的多个角部中的与所述栅电介质膜不接触的角部以外的部分的至少部分膜厚成形为小于至少部分覆盖与栅极电介质膜不接触的角部的部分的膜厚度以及覆盖电极间电介质膜的表面的第二栅电极。

88. 发明授权

US08114755B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08114755B2
公开(公告)日：2012-02-14
申请号：US12146143
申请日：2008-06-25
申请人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
发明人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
IPC分类号： H01L21/76
CPC分类号： H01L21/764
摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.
摘要翻译：一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。

89. 发明申请

US20110294304A1 Method of manufacturing semiconductor device 审中-公开
公开(公告)号：US20110294304A1
公开(公告)日：2011-12-01
申请号：US13137334
申请日：2011-08-08
申请人： Yoshio Ozawa , Akihito Yamamoto
发明人： Yoshio Ozawa , Akihito Yamamoto
IPC分类号： H01L21/316 , H01L21/318
CPC分类号： H01L21/31608 , H01L21/02164 , H01L21/02178 , H01L21/02271 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/3141 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/66825
摘要： A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine.

90. 发明申请

US20100171164A1 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100171164A1
公开(公告)日：2010-07-08
申请号：US12659703
申请日：2010-03-17
申请人： Yoshio Ozawa , Ichiro Mizushima , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi
发明人： Yoshio Ozawa , Ichiro Mizushima , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.
摘要翻译：一种非易失性半导体存储器件，包括具有半导体层和设置在其表面上的绝缘材料的半导体衬底，绝缘材料的表面被半导体层覆盖，并且设置在半导体层上的多个存储单元，存储器电池包括通过覆盖半导体层的表面而提供的第一电介质膜，设置在绝缘材料上方和第一电介质膜上的多个电荷存储层，设置在每个电荷存储层上的多个第二电介质膜，多个设置在每个第二电介质膜上的导电层，以及杂质扩散层，其部分或整体形成在绝缘材料的至少上方和半导体层的内部，并且其底端的至少一部分由绝缘体的上表面材料。

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