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    • 81. 发明申请
    • BRUSHLESS MOTOR AND FAN UNIT
    • 无刷电机和风扇单元
    • US20100129242A1
    • 2010-05-27
    • US12696989
    • 2010-01-29
    • Suguru YamadaTakashi NagamitsuYoshihisa Kato
    • Suguru YamadaTakashi NagamitsuYoshihisa Kato
    • F04D25/06H02K11/00
    • F04D25/0633F04D25/064F04D25/0646H02K3/522H02K7/14H02K11/33H02K2211/03
    • [Summary] [Object] A method to hook a magnet wire extracted from a coil[Means to Solve Problems] A stator core 35 includes a core back 352 of a substantially annular shape. At a radially outer end portion of the core back 352 four teeth 351 are arranged radially. At the teeth 351, a coil 371 is formed by winding a magnet wire 37 via an insulator 36. A first insulator 361 configuring a lower half of the insulator 36 includes a first core back insulating portion 3611, 1 first teeth insulating portion 3612, and a first cylindrical portion 3613. A hook portion 4 is formed at the first core back insulating portion 3611 at radially outer side, and between the teeth 351. The magnet wire 37 extracted from the coil 371 is hooked on the hook portion 4. The magnet wire 37 hooked on the hook portion 4 is lead the magnet wire 37 around the hook portion 4 as a base, and is soldered to a land 381 formed above a circuit board 38.
    • 摘要:一种钩绕从线圈提取的电磁线的方法[解决问题的手段]定子芯35包括大致环形的芯背352。 在芯背352的径向外端部,四个齿351径向设置。 在齿351处,通过绝缘体36缠绕电磁线37而形成线圈371.构成绝缘体36的下半部的第一绝缘体361包括第一芯背绝缘部分3611,1第一齿绝缘部分3612和 第一圆筒部3613.在第一芯背绝缘部3611的径向外侧和齿351之间形成有钩部4.钩部41上钩住从线圈371抽出的磁线37.磁体 钩在钩部4上的线37以作为基底的钩部4的方式引导电磁线37,并且焊接到形成在电路基板38上方的台阶381。
    • 87. 发明授权
    • Semiconductor memory and method for driving the same
    • 半导体存储器及其驱动方法
    • US06753560B2
    • 2004-06-22
    • US09891214
    • 2001-06-26
    • Yoshihisa KatoYasuhiro Shimada
    • Yoshihisa KatoYasuhiro Shimada
    • H01L2976
    • H01L27/11502G11C11/22H01L28/55
    • A semiconductor memory of this invention is composed of an MFMIS transistor including a first field effect transistor and a ferroelectric capacitor formed on or above the first field effect transistor with a gate electrode of the first field effect transistor working as or being electrically connected to a lower electrode of the ferroelectric capacitor, an upper electrode of the ferroelectric capacitor working as a control gate and the first field effect transistor having a first well region; and a second field effect transistor having a second well region that is isolated from the first well region of the first field effect transistor. The first well region of the first field effect transistor is electrically connected to the source region of the second field effect transistor, and the gate electrode of the first field effect transistor is electrically connected to the drain region of the second field effect transistor.
    • 本发明的半导体存储器由包括形成在第一场效应晶体管上或第一场效应晶体管上的第一场效应晶体管和铁电电容器的MFMIS晶体管组成,其中第一场效应晶体管的栅电极用作或与下电 铁电电容器的电极,作为控制栅极的铁电电容器的上电极和具有第一阱区的第一场效应晶体管; 以及具有与第一场效应晶体管的第一阱区隔离的第二阱区的第二场效应晶体管。 第一场效应晶体管的第一阱区电连接到第二场效应晶体管的源极区域,第一场效应晶体管的栅极电连接到第二场效应晶体管的漏极区域。
    • 89. 发明授权
    • Semiconductor memory and method for driving the same
    • 半导体存储器及其驱动方法
    • US06449185B2
    • 2002-09-10
    • US09886995
    • 2001-06-25
    • Yoshihisa KatoYasuhiro Shimada
    • Yoshihisa KatoYasuhiro Shimada
    • G11C1122
    • H01L27/11502G11C11/22H01L27/11585H01L27/1159
    • A semiconductor memory includes a storing transistor for storing data, wherein the storing transistor includes an MFS transistor, an MFIS transistor, or an MFMIS transistor, and a selecting transistor for selecting the storing transistor. The storing transistor is a first field effect transistor having a first well region. The selecting transistor is second field effect transistor having a second well region that is isolated from the first well region of the first field effect transistor. The semiconductor memory further includes a first voltage supply line for supplying a DC voltage to the first well region of the first field effect transistor, and a second voltage supply line, independent of the first voltage supply line, for supplying a DC voltage to the second well region of the second field effect transistor.
    • 半导体存储器包括用于存储数据的存储晶体管,其中存储晶体管包括MFS晶体管,MFIS晶体管或MFMIS晶体管,以及用于选择存储晶体管的选择晶体管。 存储晶体管是具有第一阱区的第一场效应晶体管。 选择晶体管是具有与第一场效应晶体管的第一阱区隔离的第二阱区的第二场效应晶体管。 半导体存储器还包括用于向第一场效应晶体管的第一阱区域提供DC电压的第一电压供应线和独立于第一电压供应线的第二电压供应线,用于向第二场效应晶体管提供DC电压 第二场效应晶体管的阱区。
    • 90. 发明授权
    • Method for driving semiconductor memory
    • 驱动半导体存储器的方法
    • US06421268B2
    • 2002-07-16
    • US09899839
    • 2001-07-09
    • Yoshihisa KatoYasuhiro Shimada
    • Yoshihisa KatoYasuhiro Shimada
    • G11C1122
    • G11C11/22
    • A multi-valued data is written in a ferroelectric capacitor, which stores a multi-valued data in accordance with displacement of polarization of a ferroelectric film thereof, by applying a relatively high first writing voltage or a relatively low second writing voltage between a first electrode and a second electrode of the ferroelectric capacitor. Next, a potential difference induced between the first and second electrodes is removed. Then, the multi-valued data is read by detecting the displacement of the polarization of the ferroelectric film by applying a reading voltage between the second electrode and a substrate where a reading FET for detecting the displacement of the polarization of the ferroelectric film is formed. The reading voltage has the same polarity as the first writing voltage and is set to such magnitude that, in applying the reading voltage, a first potential difference induced between the gate electrode of the reading FET and the substrate when the multi-valued data is written by applying the first writing voltage is smaller than a second potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the second writing voltage.
    • 多值数据被写入铁电电容器中,该铁电电容器通过在第一电极之间施加相对较高的第一写入电压或相对较低的第二写入电压来存储根据其铁电体膜的极化位移的多值数据 和铁电电容器的第二电极。 接下来,去除在第一和第二电极之间引起的电位差。 然后,通过在第二电极和衬底之间施加读取电压来检测强电介质膜的偏振的位移来读取多值数据,其中形成用于检测强电介质膜的偏振位移的读取FET。 读取电压具有与第一写入电压相同的极性,并且被设置为使得在施加读取电压时,当写入多值数据时,在读取FET的栅电极和衬底之间感应的第一电位差 通过施加第一写入电压小于通过施加第二写入电压来写入多值数据时在栅电极和衬底之间感应的第二电位差。