专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07554144B2 Memory device and manufacturing method 有权
标题翻译：存储器件及制造方法
公开(公告)号：US07554144B2
公开(公告)日：2009-06-30
申请号：US11279945
申请日：2006-04-17
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L29/417
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface segment and in contact with the electrodes to define an inter-electrode path defined at least in part by the length of the surface segment. According to a method for making a memory cell device, the tapering surfaces may be created by depositing a dielectric material cap using a high density plasma (HDP) deposition procedure. The electrodes and the dielectric material cap may he planarized to create the surface segment on the dielectric material. At least one of the dielectric material depositing step and the planarizing step may be controlled so that the length of the surface and segment is within a chosen dimensional range, such as between 10 nm and 100 nm.
摘要翻译：存储器件包括由绝缘构件隔开的第一和第二电极，包括由表面段连接的向上和向内的渐缩表面。包括可通过施加能量在电性能状态之间切换的记忆材料（例如相变材料）的桥被定位在表面段上并与电极接触以限定至少部分地由表面段的长度。根据制造存储单元器件的方法，可以通过使用高密度等离子体（HDP）沉积程序沉积介电材料盖而产生锥形表面。电极和电介质材料盖可以被平坦化以在电介质材料上产生表面段。可以控制介电材料沉积步骤和平坦化步骤中的至少一个，使得表面和段的长度在选定的尺寸范围内，例如在10nm和100nm之间。

82. 发明申请

US20090154222A1 OPERATION METHOD FOR MULTI-LEVEL SWITCHING OF METAL-OXIDE BASED RRAM 有权
标题翻译：基于金属氧化物的RRAM的多级开关操作方法
公开(公告)号：US20090154222A1
公开(公告)日：2009-06-18
申请号：US12388655
申请日：2009-02-19
申请人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Wei-Chih Chien , Kuo-Pin Chang , Yi-Chou Chen , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/14 , G11C11/54 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2213/32 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states to a second resistance state in the plurality of resistance states. The sequence of bias arrangements comprise a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.
摘要翻译：这里描述了用于操作这样的设备的存储器件和方法。本文描述的用于操作存储器件的方法包括：在所选择的金属氧化物存储元件上施加偏置布置序列，以将电阻状态从多个电阻状态中的第一电阻状态改变为多个电阻状态中的第二电阻状态阻力状态。偏置装置的顺序包括一个或多个脉冲的第一组，以将所选择的金属氧化物存储元件的电阻状态从第一电阻状态改变到第三电阻状态;以及第二组一个或多个脉冲，以改变所选择的金属氧化物存储元件从第三电阻状态到第二电阻状态的电阻状态。

83. 发明申请

US20090072211A1 Resistive random access memory and method for manufacturing the same 有权
标题翻译：电阻随机存取存储器及其制造方法
公开(公告)号：US20090072211A1
公开(公告)日：2009-03-19
申请号：US11898529
申请日：2007-09-13
申请人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1633
摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.
摘要翻译：提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。绝缘层设置在底部电极上。绝缘层具有第一宽度的接触孔。硬掩模层具有开口。存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。顶部电极设置在绝缘层上并与存储单元耦合。

84. 发明申请

US20090032793A1 Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact 有权
标题翻译：电阻随机存取存储器结构具有定义的小面积的电触点
公开(公告)号：US20090032793A1
公开(公告)日：2009-02-05
申请号：US11833563
申请日：2007-08-03
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144
摘要： A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.
摘要翻译：包括能够通过施加能量在电性能状态之间切换的存储材料的存储单元装置包括第一和第二电极，与第二电极电接触的存储材料（例如相变材料）插头以及由电介质形式支撑并与第一电极和记忆材料塞电接触的导电膜。电介质形式在第一电极附近较宽，在相变插头附近较窄。导电膜与相变插塞的接触面积部分地由形成导电膜的电介质形状的几何形状限定。此外，制造该器件的方法包括在第一电极上构建电介质形式，以及在电介质形式上形成导电膜的步骤。

85. 发明申请

US20080285330A1 METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES 有权
标题翻译：具有多个存储层和多个存储器状态的双向电阻随机存取存储器的操作方法
公开(公告)号：US20080285330A1
公开(公告)日：2008-11-20
申请号：US12134117
申请日：2008-06-05
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsien
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsien
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C17/165 , B82Y10/00 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C17/16 , G11C2213/31 , G11C2213/32 , G11C2213/77
摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.
摘要翻译：描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。逻辑“0”状态由数学表达式（1 + f）R表示。逻辑“1”状态为由数学表达式（n + f）R表示。逻辑“2”状态由数学表达式（1 + nf）R表示。逻辑“3”状态由数学表达式n（1 + f）R 。

86. 发明授权

US07450423B2 Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure 有权
公开(公告)号：US07450423B2
公开(公告)日：2008-11-11
申请号：US11649348
申请日：2007-01-03
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： G11C11/34 , G11C16/06 , H01L29/94
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/0475 , G11C16/14 , H01L21/28282 , H01L29/4234 , H01L29/513
摘要： A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

87. 发明申请

US20080266940A1 Air Cell Thermal Isolation for a Memory Array Formed of a Programmable Resistive Material 有权
标题翻译：用于可编程电阻材料形成的存储器阵列的空气电池热隔离
公开(公告)号：US20080266940A1
公开(公告)日：2008-10-30
申请号：US11562122
申请日：2006-11-21
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： H01L45/144 , G11C13/00 , G11C13/0004 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1293 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.
摘要翻译：存储器件包括：第一电极元件，其大体呈平面形式，具有内部接触表面。然后存在与第一电极元件间隔开的圆柱形盖层，以及具有与第一电极接触表面和盖层接触的接触表面的相变元件，其中相变元件的横向尺寸小于的第一电极元件和圆柱形盖层。第二电极元件延伸穿过盖层以与相变元件接触。与介电填充材料构成的盖层对准的侧壁在第一电极元件和盖层之间延伸，使得相变元件，第一电极元件的接触表面和侧壁限定气体充满的热隔离单元邻近相变元件。

88. 发明授权

US07442603B2 Self-aligned structure and method for confining a melting point in a resistor random access memory 有权
标题翻译：用于将熔点限制在电阻随机存取存储器中的自对准结构和方法
公开(公告)号：US07442603B2
公开(公告)日：2008-10-28
申请号：US11465094
申请日：2006-08-16
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh , Shih-Hung Chen
IPC分类号： H01L27/13
CPC分类号： H01L45/06 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
摘要翻译：制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料，选择性材料。柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

89. 发明申请

US20080173931A1 Multilevel-Cell Memory Structures Employing Multi-Memory Layers with Tungsten Oxides and Manufacturing Method 有权
标题翻译：使用氧化钨的多存储器层的多层单元存储器结构和制造方法
公开(公告)号：US20080173931A1
公开(公告)日：2008-07-24
申请号：US11625216
申请日：2007-01-19
申请人： ChiaHua Ho , Erh-Kun Lai
发明人： ChiaHua Ho , Erh-Kun Lai
IPC分类号： H01L27/00 , H01L21/44
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1633
摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
摘要翻译：本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

90. 发明申请

US20080135824A1 Method and Structure of a Multi-Level Cell Resistance Random Access Memory with Metal Oxides 有权
标题翻译：具有金属氧化物的多电平电池随机存取存储器的方法和结构
公开(公告)号：US20080135824A1
公开(公告)日：2008-06-12
申请号：US11567978
申请日：2006-12-07
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： G11C13/0016 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0014 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/1633
摘要： A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.
摘要翻译：双稳态电阻随机存取存储器的方法和结构包括多个可编程电阻随机存取存储器单元，其中每个可编程电阻随机存取存储单元包括用于为每个存储单元执行多位的多个存储器构件。双稳态RRAM包括第一电阻随机存取构件通过互连金属衬垫和金属氧化物条连接到第二电阻随机存取构件。第一电阻随机存取构件具有基于第一电阻随机存取构件的沉积从第一电阻随机存取构件的厚度确定的第一电阻值Ra。第二电阻随机存取部件具有基于第二电阻随机存取部件的沉积从第二电阻随机存取部件的厚度确定的第二电阻值Rb。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式