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81. 发明申请

US20100328830A1 Methods of achieving linear capacitance in symmetrcial and asymmetrical EMI filters with TVS 有权
标题翻译：用TVS在对称和非对称EMI滤波器中实现线性电容的方法
公开(公告)号：US20100328830A1
公开(公告)日：2010-12-30
申请号：US12807484
申请日：2010-09-07
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H02H3/22 , H01L21/82
CPC分类号： H01L27/0676 , H01L23/552 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.
摘要翻译：具有与第一导电类型的半导体衬底上支持的电磁干扰（EMI）滤波器集成的具有单向阻塞和对称双向阻塞能力的瞬态电压抑制（TVS）电路。与EMI滤波器集成的TVS电路还包括设置在用于对称双向阻塞结构的表面上的接地端子和用于单向阻塞结构的半导体衬底的底部以及设置在单向阻断结构上的输入和输出端子具有至少齐纳二极管的顶表面和设置在半导体衬底中的多个电容器，以将接地端子连接到具有直接电容耦合而不具有中间浮体区域的输入和输出端子。

82. 发明授权

US07781826B2 Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter 有权
公开(公告)号：US07781826B2
公开(公告)日：2010-08-24
申请号：US11600696
申请日：2006-11-16
申请人： Shekar Mallikararjunaswamy , Madhur Bobde
发明人： Shekar Mallikararjunaswamy , Madhur Bobde
IPC分类号： H01L276/06
CPC分类号： H01L27/0727 , H01L29/0611 , H01L29/1004 , H01L29/407 , H01L29/66303 , H01L29/7304 , H01L29/7322 , H01L29/861 , H01L29/8618 , H01L29/866 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

83. 发明申请

US20090218619A1 Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
标题翻译：自对准开槽积分型场效应晶体管（AccuFET）结构及方法
公开(公告)号：US20090218619A1
公开(公告)日：2009-09-03
申请号：US12074280
申请日：2008-03-02
申请人： Francois Hebert , Madhur Bobde , Anup Bhalla
发明人： Francois Hebert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/739 , H01L21/3205
CPC分类号： H01L29/7828 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/66666
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件。半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极电压Vgs = 0伏。

84. 发明申请

US20080218922A1 MOS transistor triggered transient voltage supressor to provide circuit protection at a lower voltage 有权
标题翻译： MOS晶体管触发瞬态电压抑制器，以在较低电压下提供电路保护
公开(公告)号：US20080218922A1
公开(公告)日：2008-09-11
申请号：US11712317
申请日：2007-02-28
申请人： Shekar Mallikararjunaswamy , Madhur Bobde
发明人： Shekar Mallikararjunaswamy , Madhur Bobde
IPC分类号： H02H3/20
CPC分类号： H01L27/0262 , Y10T29/49002
摘要： An electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering MOS transistor connected between an emitter and a collector of a first bipolar-junction transistor (BJT) coupled to a second BJT to form a SCR functioning as a main clamp circuit of the TVS circuit. The TVS circuit further includes a triggering circuit for generating a triggering signal for the triggering MOS transistor wherein the triggering circuit includes multiple stacked MOS transistors for turning into a conductive state by a transient voltage while maintaining a low leakage current.
摘要翻译：一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在与第二BJT耦合的第一双极结晶体管（BJT）的发射极和集电极之间的触发MOS晶体管，以形成用作TVS电路的主钳位电路的SCR。 TVS电路还包括用于产生用于触发MOS晶体管的触发信号的触发电路，其中触发电路包括多个堆叠的MOS晶体管，用于通过瞬态电压转变为导通状态，同时保持低的漏电流。

85. 发明申请

US20080079035A1 Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch 有权
标题翻译：对称阻塞瞬态电压抑制器（TVS）采用双极晶体管基极抢夺
公开(公告)号：US20080079035A1
公开(公告)日：2008-04-03
申请号：US11541370
申请日：2006-09-30
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L29/80
CPC分类号： H01L27/0259 , Y10T29/49002
摘要： A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
摘要翻译：用于抑制瞬态电压的对称阻塞瞬态电压抑制（TVS）电路包括具有电连接到两个晶体管的公共源的基极的NPN晶体管，由此基极连接到正或负的低电位的端子电压瞬变。两个晶体管是用于实现基本上对称的双向钳位瞬态电压的两个基本相同的晶体管。这两个晶体管还包括具有电互连源的第一和第二MOSFET晶体管。第一MOSFET晶体管还包括连接到高电位端子的漏极和连接到低电位端子的栅极，并且第二MOSFET晶体管还包括连接到低电位端子的端子的漏极和连接到高电位的栅极潜在终端。

86. 发明授权

US10468526B2 Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method 有权
公开(公告)号：US10468526B2
公开(公告)日：2019-11-05
申请号：US15836756
申请日：2017-12-08
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/265 , H01L29/417 , H01L29/45 , H01L29/47 , H01L29/08
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

87. 发明申请

US20170213887A1 INTEGRATED SCHOTTKY DIODE IN HIGH VOLTAGE SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170213887A1
公开(公告)日：2017-07-27
申请号：US15479281
申请日：2017-04-05
申请人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
发明人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
IPC分类号： H01L29/06 , H01L29/78 , H01L29/10 , H01L29/739 , H01L29/49 , H01L29/872
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/0834 , H01L29/1095 , H01L29/404 , H01L29/42368 , H01L29/4916 , H01L29/512 , H01L29/66333 , H01L29/66712 , H01L29/7393 , H01L29/7395 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

88. 发明申请

US20170179107A1 TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED BREAKDOWN VOLTAGE 有权
公开(公告)号：US20170179107A1
公开(公告)日：2017-06-22
申请号：US15445640
申请日：2017-02-28
申请人： Ning Shi , Lingpeng Guan , Madhur Bobde
发明人： Ning Shi , Lingpeng Guan , Madhur Bobde
IPC分类号： H01L27/02 , H01L29/66 , H01L29/87
CPC分类号： H01L27/0248 , H01L27/0255 , H01L29/0626 , H01L29/0649 , H01L29/66113 , H01L29/7424 , H01L29/86 , H01L29/87
摘要： A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.

89. 发明授权

US09685523B2 Diode structures with controlled injection efficiency for fast switching 有权
公开(公告)号：US09685523B2
公开(公告)日：2017-06-20
申请号：US14573187
申请日：2014-12-17
申请人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
发明人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
IPC分类号： H01L29/868 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/40 , H01L29/739
CPC分类号： H01L29/868 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/36 , H01L29/402 , H01L29/407 , H01L29/6609 , H01L29/66136 , H01L29/66143 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7839 , H01L29/861 , H01L29/8613 , H01L29/8725
摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

90. 发明申请

US20170141097A1 TVS Structures for High Surge AND Low Capacitance 审中-公开
公开(公告)号：US20170141097A1
公开(公告)日：2017-05-18
申请号：US14565392
申请日：2014-12-09
申请人： Madhur Bobde , Wenjiang Zeng , Limin Weng
发明人： Madhur Bobde , Wenjiang Zeng , Limin Weng
IPC分类号： H01L27/02 , H01L21/283 , H01L21/822
CPC分类号： H01L27/0248 , H01L21/283 , H01L21/822 , H01L27/0262 , H01L27/0814 , H01L29/0649 , H01L29/1016 , H01L29/43 , H01L29/456 , H01L29/66371 , H01L29/7412
摘要： A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

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