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81. 发明授权

US08649763B2 Highly secured portable telephone system and information system 失效
标题翻译：高度安全的便携式电话系统和信息系统
公开(公告)号：US08649763B2
公开(公告)日：2014-02-11
申请号：US12219898
申请日：2008-07-30
申请人： Yasuhiko Sasaki , Masashi Yano , Hideo Munehiro , Noriyuki Sugiura , Toru Ishikawa
发明人： Yasuhiko Sasaki , Masashi Yano , Hideo Munehiro , Noriyuki Sugiura , Toru Ishikawa
IPC分类号： H04M1/66
CPC分类号： H04M7/0033 , H04L63/105 , H04M7/003
摘要： In order to solve the problem in that information relating to a specific purpose can be saved in the internal memory of a mobile apparatus on which a permanent memory is mounted while information relating to other purpose cannot be saved in the internal memory of the apparatus, the purpose of each telephone call is distinguished by sending a non-telephone type notice before transferring the call and thus the user can determine whether the call should be saved or not.
摘要翻译：为了解决与特定目的相关的信息可以保存在其上安装有永久存储器的移动装置的内部存储器中，而与其他目的有关的信息不能保存在装置的内部存储器中的问题，通过在转移呼叫之前发送非电话类型通知来区分每个电话呼叫的目的，因此用户可以确定呼叫是否应该被保存。

82. 发明授权

US08404480B2 Microorganism testing device and microorganism testing chip 有权
标题翻译：微生物检测装置和微生物检测芯片
公开(公告)号：US08404480B2
公开(公告)日：2013-03-26
申请号：US12575489
申请日：2009-10-08
申请人： Kei Takenaka , Yasuhiko Sasaki , Hideki Nakamoto , Kazuo Takei , Masahiro Kurihara , Yuusuke Watanabe , Hisao Saito
发明人： Kei Takenaka , Yasuhiko Sasaki , Hideki Nakamoto , Kazuo Takei , Masahiro Kurihara , Yuusuke Watanabe , Hisao Saito
IPC分类号： C12M1/34 , G01N21/03
CPC分类号： G01N15/14 , B01L3/502707 , B01L2300/0867 , B01L2300/087 , B01L2400/0487 , G01N21/6428 , G01N2015/1452 , G01N2021/6441 , Y10T29/49826
摘要： Provided are a microorganism testing chip capable of suppressing self-fluorescence and enhancing mass productivity, and a microorganism testing device using the same. The microorganism testing chip includes a main body and a fungus body detection unit mounted on the main body. The main body has a detection window frame portion which is a through-hole or a pass-through groove. The fungus body detection unit is disposed to cover the detection window frame portion and has a fungus body detection flow path connected to flow paths provided in the main body. The fungus body detection unit includes a cover member and a flow path member, and is formed by attaching these two members to each other. The flow path member has a groove. By attaching the two members to each other, the groove of the flow path member serves as the fungus body detection flow path.
摘要翻译：提供能够抑制自发荧光并提高批量生产率的微生物测试芯片，以及使用其的微生物测试装置。微生物检测芯片包括安装在主体上的主体和真菌体检测单元。主体具有作为通孔或贯通槽的检测窗框架部。真菌体检测单元被设置为覆盖检测窗框部，并且具有连接到设置在主体中的流路的真菌体检测流路。真菌体检测单元包括盖构件和流路构件，并且通过将这两个构件彼此附接而形成。流路构件具有凹槽。通过将两个构件相互连接，流路构件的槽用作真菌体检测流路。

83. 发明授权

US07651700B2 Topical diclofenac patch 有权
标题翻译：局部双氯芬酸贴片
公开(公告)号：US07651700B2
公开(公告)日：2010-01-26
申请号：US10332978
申请日：2002-05-22
申请人： Yasuhiko Sasaki , Yukihiro Matsumura , Masaru Yamazaki , Hiroshi Arai , Shogo Kawabata , Masaaki Saito , Hirohisa Okuyama , Makoto Suzuki
发明人： Yasuhiko Sasaki , Yukihiro Matsumura , Masaru Yamazaki , Hiroshi Arai , Shogo Kawabata , Masaaki Saito , Hirohisa Okuyama , Makoto Suzuki
IPC分类号： A61F13/00 , A61F13/02 , A61L15/16
CPC分类号： A61K9/7053 , A61K9/7076 , A61K31/196
摘要： The invention provides an analgesic anti-inflammatory patch of a hydrophobic type for topical application containing, in a Pressure Sensitive Adhesive (PSA), diclofenac sodium, pyrrolidone or a derivative thereof, a polyhydric alcohol fatty acid ester, and an organic acid. The patch exerts the following effects: (1) diclofenac sodium is effectively and continuously released from a Pressure Sensitive Adhesive (PSA) and percutaneously absorbed, thereby attaining sustained, excellent pharmaceutical and pharmacological effects; (2) the patch per se has high tackiness and safety; and (3) diclofenac sodium remains stable in the Pressure Sensitive Adhesive (PSA).
摘要翻译：本发明提供一种用于局部应用的疏水型止痛抗炎贴片，其中包含压敏粘合剂（PSA），双氯芬酸钠，吡咯烷酮或其衍生物，多元醇脂肪酸酯和有机酸。补片发挥以下作用：（1）双氯芬酸钠从压敏粘合剂（PSA）中有效连续释放，经皮吸收，达到持续，优异的药理和药理作用; （2）贴片本身具有很高的粘性和安全性; 和（3）双氯芬酸钠在压敏粘合剂（PSA）中保持稳定。

84. 发明申请

US20080052430A1 Integrated Circuit Device and Signal Transmission System 失效
标题翻译：集成电路设备和信号传输系统
公开(公告)号：US20080052430A1
公开(公告)日：2008-02-28
申请号：US11630387
申请日：2004-08-04
申请人： Naoki Kato , Yasuhiko Sasaki
发明人： Naoki Kato , Yasuhiko Sasaki
IPC分类号： G06F13/42
CPC分类号： G06F13/385 , G06F13/4018
摘要： Some interface signals are selected from among signals of a plurality of different parallel interfaces, then being multiplexed onto a serial connection. A transmitter of a signal transmission system includes an interface-signal selector IFS, and a transfer programmer TP for issuing a control signal to instruct the selection from among the parallel interfaces. The transfer programmer TP implements the multiplexing of the selected interface signals in such a manner that the specification of the parallel interfaces is satisfied. Also, the transfer programmer TP changes, as occasion requires, the control signal to instruct which interfaces to select. This change allows the interface signals to be multiplexed onto the serial connection while dynamically changing the interface signals to be multiplexed.
摘要翻译：从多个不同的并行接口的信号中选择一些接口信号，然后被复用到串行连接上。信号传输系统的发射机包括接口信号选择器IFS和用于发出控制信号以从并行接口指示选择的传输编程器TP。传输编程器TP以满足并行接口的规范的方式实现所选接口信号的复用。此外，转移编程器TP根据需要改变控制信号以指示哪些接口被选择。该变化允许接口信号被多路复用到串行连接上，同时动态地改变要复用的接口信号。

85. 发明申请

US20070249039A1 MINUTE CREATURE DETECTION SYSTEM AND ANALYTIC CHIP 审中-公开
标题翻译：分钟检测系统和分析芯片
公开(公告)号：US20070249039A1
公开(公告)日：2007-10-25
申请号：US11627402
申请日：2007-01-26
申请人： Mitsuhiro Matsuzawa , Hisao Inami , Yasuhiko Sasaki , Masahiro Kurihara
发明人： Mitsuhiro Matsuzawa , Hisao Inami , Yasuhiko Sasaki , Masahiro Kurihara
IPC分类号： C12M1/34
CPC分类号： B01L3/502746 , B01L3/5027 , B01L7/52 , B01L9/527 , B01L2200/141 , B01L2300/0654 , B01L2300/0681 , B01L2300/069 , B01L2300/0816 , B01L2400/0487 , B01L2400/0688 , B01L2400/084
摘要： It is an object of the present invention to shorten the operation time from sampling through to genetic test, and enable the detection of a minute creature with good accuracy. Provided is minute creature detection system in which treatments from gene extraction to detection of are conducted on an analytic chip, in which the analytic chip 300 contains a sample reservoir 315, a gene extraction area 320 filled with a gene binding carrier, a waste solution chamber 330 filled with absorbent, a washing solution storage chamber 340 which stores washing solution, an eluenting solution storage chamber 370 which stores a gene eluenting solution, a gene-amplification reagent storage chamber 380 which stores a gene-amplification reagent, and a reaction chamber 395 which amplifies and detects the gene, each of which is formed by a channel, and a weir having a channel in at least either the sample reservoir 315 or the reagent storage chamber 380 which contracts and expands.
摘要翻译：本发明的目的是缩短从采样到遗传检测的操作时间，并且能够精确地检测微小的生物。提供了一种分析生物检测系统，其中分析芯片300在分析芯片上进行从基因提取到检测的处理，其中分析芯片300包含样品储存器315，填充有基因结合载体的基因提取区域320，废液溶液室 330，填充有吸收剂，存储洗涤溶液的洗涤溶液储存室340，存储基因洗脱溶液的洗脱溶液储存室370，存储基因扩增试剂的基因扩增试剂储存室380和反应室395 其放大并检测每个由通道形成的基因，以及在至少收集和扩展的样品储存器315或试剂储存室380中的通道的堰。

86. 发明授权

US07253670B2 Phase synchronization circuit and semiconductor integrated circuit 有权
标题翻译：相位同步电路和半导体集成电路
公开(公告)号：US07253670B2
公开(公告)日：2007-08-07
申请号：US11288176
申请日：2005-11-29
申请人： Yasuhiko Sasaki
发明人： Yasuhiko Sasaki
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03K5/135
摘要： A phase synchronization circuit comprises: a measurement delay line which includes a plurality of delay elements having different delay times and to which a first clock signal is inputted; a phase comparator line which includes a plurality of phase comparators in accordance with the measurement delay line and to which a signal from the measurement delay line and a second clock signal are inputted so as to measure a transition timing difference between the first clock signal and the second clock signal; and a generation delay line which includes a plurality of delay elements having different delay times in accordance with the measurement delay line and to which a signal from the phase comparator line and a third clock signal are inputted. The delay time of the respective delay elements is fixed.
摘要翻译：相位同步电路包括：测量延迟线，包括具有不同延迟时间的多个延迟元件，第一时钟信号被输入到该延迟元件; 相位比较器线，其包括根据测量延迟线的多个相位比较器，并且输入来自测量延迟线的信号和第二时钟信号，以便测量第一时钟信号和第二时钟信号之间的转换定时差第二时钟信号; 以及生成延迟线，其包括根据测量延迟线具有不同延迟时间的多个延迟元件，并且来自相位比较器线和第三时钟信号的信号被输入到该延迟元件。各个延迟元件的延迟时间是固定的。

87. 发明申请

US20060206629A1 Peripheral, peripheral control method, peripheral control system, memory medium for storing peripheral control program, and peripheral control program product 失效
标题翻译：外围设备，外设控制方法，外设控制系统，存储外围设备控制程序的存储介质以及外围控制程序产品
公开(公告)号：US20060206629A1
公开(公告)日：2006-09-14
申请号：US11417161
申请日：2006-05-04
申请人： Yasuhiko Sasaki , Tomoaki Endoh , Mamoru Osada , Takayuki Matsuo , Takashi Inoue , Naoko Shimotai , Tomoko Takagi
发明人： Yasuhiko Sasaki , Tomoaki Endoh , Mamoru Osada , Takayuki Matsuo , Takashi Inoue , Naoko Shimotai , Tomoko Takagi
IPC分类号： G06F3/00
CPC分类号： H04N1/00204 , H04N1/00957 , H04N1/00973 , H04N1/32502 , H04N1/32512 , H04N2201/0039 , H04N2201/0094 , H04N2201/3212
摘要： An object of the present invention is to provide a multi-function peripheral which is easy for a user to operate. To achieve the object, according to the present invention, there is provided a peripheral connected to an information processing apparatus, which inputs and analyzes a job script constituted of packet data from the information processing apparatus, and subsequently generates an appropriate job file in accordance with the content of the job script.
摘要翻译：本发明的目的是提供一种用户操作容易的多功能外围设备。为了实现该目的，根据本发明，提供了一种连接到信息处理设备的外围设备，其输入和分析来自信息处理设备的由分组数据构成的作业脚本，并且随后根据作业脚本的内容。

88. 发明授权

US06535932B1 Data processing apparatus and method in which a logical device control program analyzes an inputted job, and storage medium storing a program therefor 失效
标题翻译：数据处理装置和方法，其中逻辑设备控制程序分析输入的作业以及存储其程序的存储介质
公开(公告)号：US06535932B1
公开(公告)日：2003-03-18
申请号：US09383926
申请日：1999-08-26
申请人： Tomoaki Endoh , Mamoru Osada , Takashi Inoue , Yasuhiko Sasaki , Kan Torii , Naoko Shimotai , Tomoko Takagi
发明人： Tomoaki Endoh , Mamoru Osada , Takashi Inoue , Yasuhiko Sasaki , Kan Torii , Naoko Shimotai , Tomoko Takagi
IPC分类号： G06F300
CPC分类号： G06F3/1204 , G06F3/1244 , G06F3/1259 , G06F3/1285
摘要： There is provided a multi-functional peripheral which is easy for user to use. In the multi-functional peripheral, after a logical device control program retaining a function of a logical device to which the job is transmitted from an information processing apparatus and managing the job transmitted to the logical device is allowed to analyze the inputted job, a physical device control program retaining a function of a device engine of the peripheral and managing the job in the device engine is allowed to analyze the job.
摘要翻译：提供了一个易于使用的多功能外围设备。在多功能外围设备中，在从信息处理设备保存作业发送的逻辑设备的功能的逻辑设备控制程序和管理发送到逻辑设备的作业之后，允许对输入的作业进行分析，允许保留外围设备引擎的功能并管理设备引擎中的作业的设备控制程序来分析作业。

89. 发明授权

US06400183B2 Logic circuit and its forming method 失效
公开(公告)号：US06400183B2
公开(公告)日：2002-06-04
申请号：US09906264
申请日：2001-07-17
申请人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
发明人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki
IPC分类号： H03K19094
CPC分类号： G06F17/505 , H03K19/1737
摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

90. 发明授权

US06259276B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06259276B1
公开(公告)日：2001-07-10
申请号：US09542620
申请日：2000-04-04
申请人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
发明人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
IPC分类号： H03K19094
CPC分类号： H03K19/1736 , G06F17/505 , H03K19/1737
摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.
摘要翻译：对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系（PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

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