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81. 发明授权

US08111903B2 Inline low-damage automated failure analysis 有权
标题翻译：内联低损伤自动化故障分析
公开(公告)号：US08111903B2
公开(公告)日：2012-02-07
申请号：US12238602
申请日：2008-09-26
申请人： Steven B. Herschbein , Ronald C. Geiger, Jr. , George Y. Gu , Oleg Gluschenkov , Xu Ouyang
发明人： Steven B. Herschbein , Ronald C. Geiger, Jr. , George Y. Gu , Oleg Gluschenkov , Xu Ouyang
IPC分类号： G06K9/00
CPC分类号： G06T7/0004 , G06T2207/10061 , G06T2207/30148
摘要： A system and method for failure analysis of devices on a semiconductor wafer is disclosed. The present invention comprises the use of an inline focused ion beam milling tool to perform milling and image capturing of cross sections of a desired inspection point. The inspection points are located by identifying at least one fiducial that corresponds to an X-Y offset from the desired inspection point. The fiducials are recognized by a computer vision system. By automating the inspection process, the time required to perform the inspections is greatly reduced.
摘要翻译：公开了一种用于半导体晶片上的器件的故障分析的系统和方法。本发明包括使用在线聚焦离子束铣削工具来执行所需检查点的横截面的铣削和图像捕获。通过识别与期望的检查点的X-Y偏移对应的至少一个基准来定位检查点。基准由计算机视觉系统认可。通过自动化检查过程，进行检查所需的时间大大减少。

82. 发明授权

US07932136B2 Source/drain junction for high performance MOSFET formed by selective EPI process 有权
标题翻译：通过选择性EPI工艺形成的高性能MOSFET的源极/漏极结
公开(公告)号：US07932136B2
公开(公告)日：2011-04-26
申请号：US12109025
申请日：2008-04-24
申请人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
发明人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译：在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。

83. 发明授权

US07767503B2 Hybrid SOI/bulk semiconductor transistors 失效
标题翻译：混合SOI /体半导体晶体管
公开(公告)号：US07767503B2
公开(公告)日：2010-08-03
申请号：US12132853
申请日：2008-06-04
申请人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

84. 发明授权

US07709333B2 Method for reducing overlap capacitance in field effect transistors 失效
标题翻译：降低场效应晶体管重叠电容的方法
公开(公告)号：US07709333B2
公开(公告)日：2010-05-04
申请号：US12173098
申请日：2008-07-15
申请人： Huilong Zhu , Oleg Gluschenkov
发明人： Huilong Zhu , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/7624 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
摘要翻译：场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域仅沿着栅极导体的宽度的选定位置。

85. 发明申请

US20090146181A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS 审中-公开
标题翻译：采用扩散源/漏斗扩展的集成电路系统
公开(公告)号：US20090146181A1
公开(公告)日：2009-06-11
申请号：US11952939
申请日：2007-12-07
申请人： Chung Woh Lai , Oleg Gluschenkov , Henry K. Utomo , Lee Wee Teo , Jin Ping Liu , Anita Madan , Rainer Loesing , Jin-Ping Han , Hyung-Yoon Choi
发明人： Chung Woh Lai , Oleg Gluschenkov , Henry K. Utomo , Lee Wee Teo , Jin Ping Liu , Anita Madan , Rainer Loesing , Jin-Ping Han , Hyung-Yoon Choi
IPC分类号： H01L29/778 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.
摘要翻译：一种集成电路系统，包括：提供包括掺杂外延层的PFET器件; 以及通过使用能量源从掺杂的外延层扩散掺杂剂形成源极/漏极扩展。

86. 发明申请

US20090132985A1 Design structure for on-chip electromigration monitoring system 有权
标题翻译：片上电迁移监控系统的设计结构
公开(公告)号：US20090132985A1
公开(公告)日：2009-05-21
申请号：US11985966
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, JR. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, JR. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/2858
摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。

87. 发明申请

US20080265931A1 On-chip electromigration monitoring 有权
标题翻译：片上电迁移监测
公开(公告)号：US20080265931A1
公开(公告)日：2008-10-30
申请号：US12215732
申请日：2008-06-30
申请人： Louis L. Hsu , Hayden C. Cranford , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A method is provided for monitoring interconnect resistance within a semiconductor chip assembly. A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.
摘要翻译：提供了一种用于监测半导体芯片组件内的互连电阻的方法。半导体芯片组件可以包括具有暴露在半导体芯片的表面处的触点的半导体芯片和具有与触点导电连通的暴露端子的基板。半导体芯片的多个受监测元件可以包括导电互连，每个导体互连通过半导体芯片内的布线互连半导体芯片的相应的一对节点。在这种方法的示例中，在半导体芯片组件的寿命期间，跨越每个被监测元件的电压降与在半导体芯片上的相应参考元件上的参考电压降在多个不同时间进行比较。以这种方式，当这种被监视的元件的电阻超过阈值时，可以检测它。基于这种比较的结果，可以做出是否指示动作条件的决定。

88. 发明申请

US20080265282A1 SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：硅锗绝缘双极晶体管结构与方法
公开(公告)号：US20080265282A1
公开(公告)日：2008-10-30
申请号：US11741836
申请日：2007-04-30
申请人： Oleg Gluschenkov , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Oleg Gluschenkov , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L31/11 , H01L21/331 , H01L31/117 , H01L31/00
CPC分类号： H01L29/66242 , H01L21/2253 , H01L21/26513 , H01L21/324 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/7378
摘要： Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
摘要翻译：公开了一种改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管），其具有窄的基本上无间隙的SIC基座，其外部基极具有最小的重叠。此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。

89. 发明申请

US20080242069A1 HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 失效
标题翻译：混合SOI / BULK半导体晶体管
公开(公告)号：US20080242069A1
公开(公告)日：2008-10-02
申请号：US12132853
申请日：2008-06-04
申请人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

90. 发明授权

US07394273B2 On-chip electromigration monitoring system 有权
标题翻译：片上电迁移监控系统
公开(公告)号：US07394273B2
公开(公告)日：2008-07-01
申请号：US11306985
申请日：2006-01-18
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.
摘要翻译：提供一种封装的半导体芯片，其包括半导体芯片和封装元件。半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时被监测元件的电阻超过阈值。

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