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81. 发明申请

US20080105932A1 Partial FinFET memory cell 有权
标题翻译：部分FinFET存储单元
公开(公告)号：US20080105932A1
公开(公告)日：2008-05-08
申请号：US11588483
申请日：2006-10-27
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/1108 , H01L27/11 , H01L27/1104 , H01L29/785 , H01L29/7854
摘要： A semiconductor structure includes a semiconductor substrate, a planar PMOS device at a surface of the semiconductor substrate, and an NMOS device at the surface of the semiconductor substrate, wherein the NMOS device is a Fin field effect transistor (FinFET).
摘要翻译：半导体结构包括半导体衬底，在半导体衬底的表面处的平面PMOS器件和在半导体衬底的表面处的NMOS器件，其中NMOS器件是Fin场效应晶体管（FinFET）。

82. 发明申请

US20070200182A1 Memory array structure with strapping cells 有权
标题翻译：内存阵列结构，带有单元格
公开(公告)号：US20070200182A1
公开(公告)日：2007-08-30
申请号：US11361248
申请日：2006-02-24
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/76
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+strap between N+active areas of two memory cells in a column and provide an N+strap between P+active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.
摘要翻译：提供具有一排捆扎单元的存储器阵列。根据本发明的实施例，捆扎单元位于两行存储器阵列之间。捆扎单元在列中的两个存储单元的N +有效区之间提供P +带，并在存储器阵列的列中的两个存储单元的P +有效区之间提供N +带。带状单元在存储器阵列的两行之间提供绝缘结构，并且创建存储器单元的更均匀的操作，而不管存储器阵列内的存储器单元的位置如何。在一个实施例中，可以沿着垂直于捆扎单元行的方向沿着存储器阵列的外边缘形成虚拟N阱。此外，可以在捆扎单元中形成晶体管，以在带状存储单元之间提供额外的绝缘。

83. 发明授权

US07250657B2 Layout structure for memory arrays with SOI devices 有权
标题翻译：具有SOI器件的存储器阵列的布局结构
公开(公告)号：US07250657B2
公开(公告)日：2007-07-31
申请号：US11078745
申请日：2005-03-11
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L27/01 , H01L29/04
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The oxide defined (OD) area is formed on an insulating layer, extending across at least two neighboring SRAM cell areas for construction of a passing gate transistor and a pull-down transistor used in an SRAM cell. The strapping cell area is interposed between the SRAM cell areas, in which a strapping cell is constructed for connecting the OD area to a fixed potential, thereby preventing bodies of the passing gate transistor and the pull-down transistor constructed on the OD area from floating.
摘要翻译：静态随机存取存储器（SRAM）单元阵列的布局结构包括至少一个SRAM单元区域，氧化物定义（OD）区域和捆扎单元区域。 SRAM单元区域的纵向边比其横向方向至少长两倍。氧化物限定（OD）区域形成在绝缘层上，延伸穿过至少两个相邻的SRAM单元区域，用于构造在SRAM单元中使用的通过栅极晶体管和下拉晶体管。捆扎单元区域介于SRAM单元区域之间，其中构造了用于将OD区域连接到固定电位的捆扎单元，从而防止构成在OD区域上的通过栅极晶体管和下拉晶体管的体浮动。

84. 发明申请

US20060202361A1 Layout structure for memory arrays with SOI devices 有权
标题翻译：具有SOI器件的存储器阵列的布局结构
公开(公告)号：US20060202361A1
公开(公告)日：2006-09-14
申请号：US11078745
申请日：2005-03-11
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/76
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The oxide defined (OD) area is formed on an insulating layer, extending across at least two neighboring SRAM cell areas for construction of a passing gate transistor and a pull-down transistor used in an SRAM cell. The strapping cell area is interposed between the SRAM cell areas, in which a strapping cell is constructed for connecting the OD area to a fixed potential, thereby preventing bodies of the passing gate transistor and the pull-down transistor constructed on the OD area from floating.
摘要翻译：静态随机存取存储器（SRAM）单元阵列的布局结构包括至少一个SRAM单元区域，氧化物定义（OD）区域和捆扎单元区域。 SRAM单元区域的纵向边比其横向方向至少长两倍。氧化物限定（OD）区域形成在绝缘层上，延伸穿过至少两个相邻的SRAM单元区域，用于构造在SRAM单元中使用的通过栅极晶体管和下拉晶体管。捆扎单元区域介于SRAM单元区域之间，其中构造了用于将OD区域连接到固定电位的捆扎单元，从而防止构成在OD区域上的通过栅极晶体管和下拉晶体管的体浮动。

85. 发明申请

US20060118904A1 Fuse structure with charge protection circuit 有权
标题翻译：保险丝结构带充电保护电路
公开(公告)号：US20060118904A1
公开(公告)日：2006-06-08
申请号：US11001056
申请日：2004-12-02
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for memory cell repair in a RAM device. The fuse structure includes a substrate, a fuse layer over an isolation region on the substrate, a charge protection circuit electrically connected to one side of the fuse layer, and two conductive layers overlying the substrate and electrically connected to the charge protection circuit and the other side of the fuse layer respectively.
摘要翻译：一种用于RAM设备中的存储器单元修复的熔丝结构。熔丝结构包括衬底，衬底上的隔离区域上的熔丝层，电连接到熔丝层的一侧的电荷保护电路，以及覆盖在衬底上并电连接到电荷保护电路和另一个一侧的熔丝层。

86. 发明授权

US06992916B2 SRAM cell design with high resistor CMOS gate structure for soft error rate improvement 失效
公开(公告)号：US06992916B2
公开(公告)日：2006-01-31
申请号：US10460983
申请日：2003-06-13
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

87. 发明授权

US06214656B1 Partial silicide gate in sac (self-aligned contact) process 有权
标题翻译：囊状部分硅化物（自对准接触）工艺
公开(公告)号：US06214656B1
公开(公告)日：2001-04-10
申请号：US09313301
申请日：1999-05-17
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L218238
CPC分类号： H01L21/76897 , H01L21/823835 , H01L21/823842
摘要： A method for integrating salicide and self-aligned contact processes in the fabrication integrated circuits is described. A polysilicon layer is deposited overlying a gate oxide layer and isolation areas. Ions are implanted into the polysilicon layer to define a surface channel dual gate wherein an NMOS gate area is formed on one side of the substrate and a PMOS gate area is formed on the other side of the substrate and the junction where the NMOS gate area meets the PMOS gate area forms a CMOS gate area. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are patterned to form NMOS and PMOS gates. Optionally, an etch stop layer is deposited over the gates and associated source and drain regions. The hard mask layer is removed overlying the CMOS gate and one of the NMOS or PMOS gates where a contact is to be made to the gate. A metal layer silicide is formed where the hard mask has been removed by a salicide process. A self-aligned contact opening is formed through an insulating layer to one of the source and drain regions. A contact opening is formed through the insulating layer to the metal silicide layer overlying the gate where the contact is to be made. A conducting layer is deposited over the semiconductor substrate and within the self-aligned contact opening and within the contact opening and patterned to complete fabrication of the integrated circuit device.
摘要翻译：描述了在制造集成电路中整合自对准和自对准接触工艺的方法。沉积覆盖栅极氧化物层和隔离区的多晶硅层。将离子注入到多晶硅层中以限定表面沟道双栅极，其中NMOS栅极区域形成在衬底的一侧上，并且PMOS栅极区域形成在衬底的另一侧和NMOS栅极区域遇到的结 PMOS栅极区域形成CMOS栅极区域。覆盖多晶硅层的硬掩模层被沉积。图案化硬掩模和多晶硅层以形成NMOS和PMOS栅极。可选地，蚀刻停止层沉积在栅极和相关联的源极和漏极区域上。去除硬掩模层，覆盖CMOS栅极和NMOS或PMOS栅极之一，其中将形成与栅极的接触。形成金属层硅化物，其中通过自对准硅化物工艺去除硬掩模。自对准的接触开口通过绝缘层形成到源区和漏区之一。形成穿过绝缘层的接触开口与覆盖在要接触的栅极上的金属硅化物层。导电层沉积在半导体衬底上并且在自对准接触开口内并且在接触开口内并被图案化以完成集成电路器件的制造。

88. 发明授权

US06172411B2 Self-aligned contact structures using high selectivity etching 有权
标题翻译：使用高选择性蚀刻的自对准接触结构
公开(公告)号：US06172411B2
公开(公告)日：2001-01-09
申请号：US09208921
申请日：1998-12-10
申请人： Li-chih Chao , Jhon-Jhy Liaw , Yuan-Chang Huang , Jin-Yuan Lee
发明人： Li-chih Chao , Jhon-Jhy Liaw , Yuan-Chang Huang , Jin-Yuan Lee
IPC分类号： H01L27088
CPC分类号： H01L21/76897 , H01L21/31116 , Y10S257/90
摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.
摘要翻译：描述了自对准结构和蚀刻自对准结构中的接触孔的方法。选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。氧化硅层沉积在蚀刻停止层上。使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率至少两个。

89. 发明授权

US6080647A Process to form a trench-free buried contact 失效
标题翻译：形成无沟槽埋层接触的工艺
公开(公告)号：US6080647A
公开(公告)日：2000-06-27
申请号：US34927
申请日：1998-03-05
申请人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
发明人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
IPC分类号： H01L21/336 , H01L21/768 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/76895 , H01L29/66545
摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。在半导体衬底的表面上设置栅极氧化硅层。沉积在栅极氧化物层上的多晶硅层。覆盖多晶硅层的硬掩模层被沉积。硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。介电材料层沉积在衬底上以填充间隙。去除了掩模层。此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。将离子注入到开口内的半导体衬底中以形成掩埋接触。选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

90. 发明授权

US6013547A Process for creating a butt contact opening for a self-aligned contact structure 失效
标题翻译：用于产生用于自对准接触结构的对接接触开口的方法
公开(公告)号：US6013547A
公开(公告)日：2000-01-11
申请号：US58121
申请日：1998-04-10
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823475 , H01L27/11
摘要： A method for fabricating a memory device, using a butt contact opening, and an overlying SAC structure, to allow connection between a gate structure, and an active device region, in a semiconductor substrate, has been developed. This invention features the use of an organic layer, protecting regions of the memory device from an dry etch procedure, that is used to remove insulator from the top surface, of a portion of the gate structure. A SAC structure, in a SAC opening, supplies the desired connection, via contact to both an active device region, and to the portion of gate structure, that is without the capping insulator.
摘要翻译：已经开发了一种用于制造使用对接触点开口的存储器件和覆盖SAC结构以允许半导体衬底中的栅极结构和有源器件区域之间的连接的方法。本发明的特征在于使用有机层，保护存储器件的区域不被干蚀刻过程用于从栅极结构的一部分的顶表面去除绝缘体。在SAC开口中的SAC结构通过接触向有源器件区域提供所需的连接，并且将栅极结构的不具有封盖绝缘体的部分提供给所需的连接。

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