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81. 发明申请

US20050104139A1 Method of forming fet with T-shaped gate 有权
标题翻译：用T形门形成胎儿的方法
公开(公告)号：US20050104139A1
公开(公告)日：2005-05-19
申请号：US11005659
申请日：2004-12-07
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Edward Nowak
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Edward Nowak
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/2807 , H01L21/28114 , H01L21/28123 , H01L29/1045 , H01L29/42376 , H01L29/4966 , H01L29/4991 , H01L29/7833
摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.
摘要翻译： FET具有T形门。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。两层被图案化在一起。然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。在另一个实施例中，栅极由单个栅极导体形成。金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。蚀刻硅化物以提供凹口。

82. 发明申请

US20070235811A1 Simultaneous conditioning of a plurality of memory cells through series resistors 审中-公开
标题翻译：通过串联电阻同时调节多个存储单元
公开(公告)号：US20070235811A1
公开(公告)日：2007-10-11
申请号：US11400596
申请日：2006-04-07
申请人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
发明人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
IPC分类号： H01L21/336
CPC分类号： H01L27/0629 , H01L27/101 , H01L27/24
摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.
摘要翻译：公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

83. 发明申请

US20070212810A1 MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS 有权
标题翻译：存储器件和通过在大量存储器单元中同时调节过渡金属氧化物层来制造器件的方法
公开(公告)号：US20070212810A1
公开(公告)日：2007-09-13
申请号：US11748579
申请日：2007-05-15
申请人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
发明人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , H01L27/115 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , Y10S438/90
摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
摘要翻译：公开了包含一系列单个或双重存储器单元的非易失性存储器件。单个存储器单元基本上是“U”形的。双重存储单元包括两个基本上“U”形的存储单元。每个存储单元包括具有夹在两个导电层之间的双稳态层的存储元件。临时导体可以应用于一系列的电池并且用于批量地调节电池的双稳态层。此外，由于电池的“U”形状，可以使用交叉点线阵列来连接一系列电池。交叉点线阵列允许每个单元的存储元件被单独识别和寻址用于存储信息，并且还允许使用块擦除处理同时擦除存储在串联中的所有单元中的存储器元件中的信息。

84. 发明申请

US20060195285A1 CANARY DEVICE FOR FAILURE ANALYSIS 失效
标题翻译：用于故障分析的CANARY设备
公开(公告)号：US20060195285A1
公开(公告)日：2006-08-31
申请号：US10906590
申请日：2005-02-25
申请人： Pierre Bouchard , Mark Hakey , Mark Masters , Leah Pastel , James Slinkman , David Vallett
发明人： Pierre Bouchard , Mark Hakey , Mark Masters , Leah Pastel , James Slinkman , David Vallett
IPC分类号： G06F19/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit (IC) during fabrication thereof, wherein the diagnostic system comprises at least one IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip and comprising a known electrical signature and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit indicates that the IC chip is mis-designed. The diagnostic system further comprises a semiconductor wafer comprising a plurality of IC chips and a kerf area separating one IC chip from another IC chip. The sacrificial circuit is located in the kerf area or alternatively on each of the plurality of IC chips. A mis-designed IC chip comprises abnormally functioning circuitry.
摘要翻译：一种用于在其制造期间测试集成电路（IC）的诊断系统和方法，其中所述诊断系统包括至少一个包括电特征的IC芯片; 邻近于IC芯片的牺牲电路，包括已知的电气签名和故意错误设计的电路; 以及比较器，用于将IC芯片的电气签名与牺牲电路的已知电气签名进行比较，其中IC芯片的电子签名与牺牲电路的已知电气签名的匹配表明IC芯片是错误的设计。诊断系统还包括半导体晶片，其包括多个IC芯片和将IC芯片与另一IC芯片分开的切口区域。牺牲电路位于切口区域中，或者替代地位于多个IC芯片中的每一个上。错误设计的IC芯片包括异常功能的电路。

85. 发明申请

US20070197010A1 INTEGRATED CARBON NANOTUBE SENSORS 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US20070197010A1
公开(公告)日：2007-08-23
申请号：US11696370
申请日：2007-04-04
申请人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
发明人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
IPC分类号： H01L21/3205
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

86. 发明申请

US20050287764A1 Method of fabricating shallow trench isolation by ultra-thin simox processing 审中-公开
标题翻译：通过超薄simox加工制造浅沟槽隔离的方法
公开(公告)号：US20050287764A1
公开(公告)日：2005-12-29
申请号：US11208360
申请日：2005-08-19
申请人： Bruce Doris , Mark Hakey , Akihisa Sekiguchi
发明人： Bruce Doris , Mark Hakey , Akihisa Sekiguchi
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76237 , H01L21/76243 , H01L21/76267
摘要： The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.
摘要翻译：本发明提供了在半导体衬底中形成隔离区域（例如浅沟槽隔离区域）的成本有效和简单的方法，其避免了蚀刻到沟槽中。在本发明中，通过利用在衬底的上表面附近产生氧注入区的选择性离子注入工艺来形成隔离区。在随后的退火步骤中，氧注入区域被转换成具有与衬底的上表面基本上共面的上表面的隔离区域。

87. 发明申请

US20060038167A1 INTEGRATED CARBON NANOTUBE SENSORS 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US20060038167A1
公开(公告)日：2006-02-23
申请号：US10711083
申请日：2004-08-20
申请人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
发明人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
IPC分类号： H01L31/072
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

88. 发明申请

US20060035460A1 Wiring structure for integrated circuit with reduced intralevel capacitance 有权
标题翻译：具有降低的体积电容的集成电路的接线结构
公开(公告)号：US20060035460A1
公开(公告)日：2006-02-16
申请号：US11203944
申请日：2005-08-15
申请人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
发明人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

89. 发明申请

US20050239284A1 WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE 审中-公开
标题翻译：具有降低入口电容的集成电路接线结构
公开(公告)号：US20050239284A1
公开(公告)日：2005-10-27
申请号：US10709204
申请日：2004-04-21
申请人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
发明人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

90. 发明申请

US20050090080A1 Patterned SOI by oxygen implantation and annealing 有权
标题翻译：通过氧气注入和退火进行图案化SOI
公开(公告)号：US20050090080A1
公开(公告)日：2005-04-28
申请号：US10993270
申请日：2004-11-19
申请人： Keith Fogel , Mark Hakey , Steven Holmes , Devendra Sadana , Ghavam Shahidi
发明人： Keith Fogel , Mark Hakey , Steven Holmes , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L27/08 , H01L21/02 , H01L21/20 , H01L21/265 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76243 , H01L21/26506 , H01L21/76267 , Y10T428/12674 , Y10T428/12681
摘要： Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.
摘要翻译：提供了在含Si衬底中形成图案化SOI区的方法，其具有约0.25μm或更小的几何形状。具体而言，一种方法包括以下步骤：在含Si衬底的表面上形成图案化电介质掩模，其中，图案化电介质掩模包括垂直边缘，其限定至少一个露出一部分含Si衬底的开口的边界 ; 通过所述至少一个开口注入氧离子，去除所述掩模并在至少所述含Si衬底的暴露表面上形成Si层; 并在约1250℃或更高的温度下和在氧化环境中进行退火，以便在含Si衬底中形成至少一个离散的掩埋氧化物区域。在一个实施例中，直到退火步骤之后，掩模才被去除; 并且在另一个实施方案中，在退火和掩模去除之后形成含Si层。

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