专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060267086A1 Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells 有权
公开(公告)号：US20060267086A1
公开(公告)日：2006-11-30
申请号：US11140780
申请日：2005-05-31
申请人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
发明人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
IPC分类号： H01L29/76
CPC分类号： H01L27/101 , H01L27/115 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , Y10S438/90
摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

2. 发明申请

US20070235811A1 Simultaneous conditioning of a plurality of memory cells through series resistors 审中-公开
标题翻译：通过串联电阻同时调节多个存储单元
公开(公告)号：US20070235811A1
公开(公告)日：2007-10-11
申请号：US11400596
申请日：2006-04-07
申请人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
发明人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
IPC分类号： H01L21/336
CPC分类号： H01L27/0629 , H01L27/101 , H01L27/24
摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.
摘要翻译：公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

3. 发明申请

US20070212810A1 MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS 有权
标题翻译：存储器件和通过在大量存储器单元中同时调节过渡金属氧化物层来制造器件的方法
公开(公告)号：US20070212810A1
公开(公告)日：2007-09-13
申请号：US11748579
申请日：2007-05-15
申请人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
发明人： Toshijaru Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Chung Lam , Gerhard Meijer
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , H01L27/115 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , Y10S438/90
摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
摘要翻译：公开了包含一系列单个或双重存储器单元的非易失性存储器件。单个存储器单元基本上是“U”形的。双重存储单元包括两个基本上“U”形的存储单元。每个存储单元包括具有夹在两个导电层之间的双稳态层的存储元件。临时导体可以应用于一系列的电池并且用于批量地调节电池的双稳态层。此外，由于电池的“U”形状，可以使用交叉点线阵列来连接一系列电池。交叉点线阵列允许每个单元的存储元件被单独识别和寻址用于存储信息，并且还允许使用块擦除处理同时擦除存储在串联中的所有单元中的存储器元件中的信息。

4. 发明申请

US20050260839A1 Non-volatile resistance switching memory 有权
标题翻译：非易失性电阻切换存储器
公开(公告)号：US20050260839A1
公开(公告)日：2005-11-24
申请号：US11105849
申请日：2005-04-14
申请人： Rolf Allenspach , Johannes Bednorz , Gerhard Meijer , Chung Lam , Richard Stutz , Daniel Widmer
发明人： Rolf Allenspach , Johannes Bednorz , Gerhard Meijer , Chung Lam , Richard Stutz , Daniel Widmer
IPC分类号： C23C16/40 , G11C11/56 , H01L21/02 , H01L21/20 , H01L21/316 , H01L21/8238 , H01L21/8246 , H01L27/10 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L21/31691 , H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625
摘要： Processes, apparatus and systems for depositing a switching material that is switchable between conductivity states and where the states are persistent. The invention further relates to a microelectronic device or non-volatile resistance switching memory comprising the switching material for storing digital information. A process includes a step of depositing the switching material by a CMOS deposition technique at a temperature lower than 400° C.
摘要翻译：用于沉积切换材料的过程，装置和系统，其可在导电状态之间切换，并且状态持续存在。本发明还涉及包括用于存储数字信息的切换材料的微电子装置或非易失性电阻切换存储器。一种方法包括通过CMOS沉积技术在低于400℃的温度下沉积开关材料的步骤。

5. 发明申请

US20060027893A1 Field-enhanced programmable resistance memory cell 失效
标题翻译：现场增强型可编程电阻存储单元
公开(公告)号：US20060027893A1
公开(公告)日：2006-02-09
申请号：US11176173
申请日：2005-07-07
申请人： Gerhard Meijer , Chung Lam , Hon-Sum Wong
发明人： Gerhard Meijer , Chung Lam , Hon-Sum Wong
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L45/04 , H01L27/20 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/147 , H01L45/16
摘要： Provides a field-enhanced programmable resistance memory cell. In an example embodiment, a resistor includes a resistance structure between a first electrode and a second electrode. The resistance structure includes an insulating dielectric material. The second electrode includes a protrusion extending into the resistance structure. The insulating dielectric material includes a material in which a confined conductive region with a programmable resistance is formable via a conditioning signal.
摘要翻译：提供一个场增强型可编程电阻存储单元。在示例性实施例中，电阻器包括在第一电极和第二电极之间的电阻结构。电阻结构包括绝缘介电材料。第二电极包括延伸到电阻结构中的突起。绝缘电介质材料包括其中通过调节信号可形成具有可编程电阻的受限导电区域的材料。

6. 发明申请

US20070187829A1 Nonvolatile memory cell comprising a chalcogenide and a transition metal oxide 有权
标题翻译：包含硫族化物和过渡金属氧化物的非挥发性存储单元
公开(公告)号：US20070187829A1
公开(公告)日：2007-08-16
申请号：US11353419
申请日：2006-02-14
申请人： Chung Lam , Gerhard Meijer , Alejandro Schrott
发明人： Chung Lam , Gerhard Meijer , Alejandro Schrott
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L45/145 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C2213/32 , H01L45/04
摘要： A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.
摘要翻译：用于集成电路的存储单元包括硫族化物特征和过渡金属氧化物特征。硫族化物特征和过渡金属氧化物特征都具有至少两个稳定的电阻状态。通过将硫族化物特征置于其稳定的电阻状态之一并且将过渡金属氧化物特征置于其稳定的电阻状态之一中，可将至少两位数据同时存储在存储单元中。

7. 发明申请

US20070274125A1 Enhanced Programming Performance in a Nonvolatile Memory Device Having a Bipolar Programmable Storage Element 审中-公开
标题翻译：具有双极可编程存储元件的非易失性存储器件中的增强的编程性能
公开(公告)号：US20070274125A1
公开(公告)日：2007-11-29
申请号：US11839239
申请日：2007-08-15
申请人： Johannes Bednorz , John DeBrosse , Chung Lam , Gerhard Meijer , Jonathan Sun
发明人： Johannes Bednorz , John DeBrosse , Chung Lam , Gerhard Meijer , Jonathan Sun
IPC分类号： G11C11/411
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/79
摘要： A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.
摘要翻译：非易失性存储单元包括可操作地存储存储单元的逻辑状态的双极可编程存储元件和包括第一和第二源极/漏极和栅极的金属氧化物半导体器件。双极可编程存储元件的第一端子适于连接到第一位线。第一源极/漏极连接到双极可编程存储元件的第二端子，第二源极/漏极适于连接到第二位线，并且栅极适于连接到字线。

8. 发明申请

US20070247893A1 Non-volatile memory architecture employing bipolar programmable resistance storage elements 有权
标题翻译：采用双极可编程电阻存储元件的非易失性存储架构
公开(公告)号：US20070247893A1
公开(公告)日：2007-10-25
申请号：US11409440
申请日：2006-04-21
申请人： Johannes Bednorz , Chung Lam , Gerhard Meijer
发明人： Johannes Bednorz , Chung Lam , Gerhard Meijer
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C11/1655 , G11C11/1657
摘要： A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines. At least one of the memory cells includes a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to one of a corresponding first one of the bit lines and a corresponding first one of the source lines, and a metal-oxide-semiconductor device including first and second source/drains and a gate. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a corresponding second one of the bit lines, and the gate is adapted for connection to a corresponding one of the word lines. For at least a subset of the plurality of memory cells, each pair of adjacent memory cells along a given word line shares either the same bit line or the same source line.
摘要翻译：非易失性存储器阵列包括多个字线，多个位线，多条源极线和多个非易失性存储器单元。多个存储单元的至少一个子集中的每一个具有连接到多个字线之一的第一端子，连接到多个位线之一的第二端子和连接到多个位线之一的第三端子源线。存储器单元中的至少一个包括可操作以存储存储单元的逻辑状态的双极可编程存储元件，双极可编程存储元件的第一端连接到相应的第一位线之一和相应的第一个的源极线以及包括第一和第二源极/漏极和栅极的金属氧化物半导体器件。第一源极/漏极连接到双极可编程存储元件的第二端子，第二源极/漏极适于连接到对应的第二位线，并且栅极适于连接到相应的一个字线。对于多个存储器单元的至少一个子集，沿着给定字线的每对相邻存储器单元共享相同的位线或相同的源极线。

9. 发明申请

US20060256611A1 Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element 失效
标题翻译：具有双极可编程存储元件的非易失性存储器件中的增强的编程性能
公开(公告)号：US20060256611A1
公开(公告)日：2006-11-16
申请号：US11216518
申请日：2005-08-31
申请人： Johannes Bednorz , John DeBrosse , Chung Lam , Gerhard Meijer , Jonathan Sun
发明人： Johannes Bednorz , John DeBrosse , Chung Lam , Gerhard Meijer , Jonathan Sun
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/79
摘要： A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.
摘要翻译：非易失性存储单元包括可操作地存储存储单元的逻辑状态的双极可编程存储元件和包括第一和第二源极/漏极和栅极的金属氧化物半导体器件。双极可编程存储元件的第一端子适于连接到第一位线。第一源极/漏极连接到双极可编程存储元件的第二端子，第二源极/漏极适于连接到第二位线，并且栅极适于连接到字线。

10. 发明申请

US20060071272A1 Programmable non-volatile resistance switching device 有权
标题翻译：可编程非易失性电阻开关器件
公开(公告)号：US20060071272A1
公开(公告)日：2006-04-06
申请号：US11239495
申请日：2005-09-29
申请人： Santos Alvarado , Johannes Bednorz , Gerhard Meijer
发明人： Santos Alvarado , Johannes Bednorz , Gerhard Meijer
IPC分类号： H01L29/76
CPC分类号： G11C13/0007 , G11C13/0004 , G11C19/00 , G11C2213/31 , H01L27/24
摘要： A memory element comprises a first number of electrodes and a second number of electrically conducting channels between sub-groups of two of said electrodes, the channels exhibiting an electrical resistance that is reversibly switchable between different states, wherein the first number is larger than two and the second number is larger than the first number divided by two. The electrically conducting channels may be provided in transition metal oxide material, which exhibits a reversibly switchable resistance that is attributed to a switching phenomenon at the interfaces between the electrodes and the transition metal oxide material.
摘要翻译：存储元件包括在两个所述电极的子组之间的第一数量的电极和第二数量的导电通道，所述通道呈现在不同状态之间可逆地切换的电阻，其中第一数量大于2，第二个数字大于第一个数字除以2。导电通道可以设置在过渡金属氧化物材料中，其呈现出由电极和过渡金属氧化物材料之间的界面处的切换现象引起的可逆切换电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式