专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07649780B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07649780B2
公开(公告)日：2010-01-19
申请号：US12040457
申请日：2008-02-29
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5642
摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

82. 发明授权

US07509566B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07509566B2
公开(公告)日：2009-03-24
申请号：US11747225
申请日：2007-05-10
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： H03M13/00 , G11C29/00 , G11C11/34
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

83. 发明授权

US06545909B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06545909B2
公开(公告)日：2003-04-08
申请号：US10094215
申请日：2002-03-11
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.
摘要翻译：存储单元阵列，其中存储单元可存储多级数据以矩阵形式排列。位线控制器具有被配置为锁存写入数据和被配置为感测读取数据的感测电路的锁存电路。位线连接位线控制器和存储单元。在数据写入模式期间，位线将写入数据从锁存电路提供给存储器单元，并且在数据读取模式期间将读取数据从存储器单元提供给读出电路。多级数据的数量为4，感测电路的数量为2，多级数据的数量为8，感测电路的数量为3。

84. 发明授权

US06249479B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06249479B1
公开(公告)日：2001-06-19
申请号：US09671293
申请日：2000-09-27
申请人： Toru Tanzawa , Tomoharu Tanaka
发明人： Toru Tanzawa , Tomoharu Tanaka
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A semiconductor memory device comprises a memory cell array with a plurality of blocks having a plurality of memory cells arranged in a matrix, a plurality of address latch circuits provided so as to correspond to the blocks, a row decoder that accesses the memory cell array in blocks according to the latched state of the plurality of address latch circuits, and a control circuit for accessing the memory cell array by latching all of the blocks to the selected state and then canceling the address latching of the selected block to the unselected state.
摘要翻译：一种半导体存储器件包括具有多个块的存储单元阵列，多个块具有以矩阵形式排列的多个存储单元，多个地址锁存电路被提供以对应于这些块，行解码器访问存储单元阵列根据多个地址锁存电路的锁存状态的块，以及用于通过将所有块锁定到选择状态并随后将所选择的块的地址锁存取消为未选择状态来访问存储单元阵列的控制电路。

85. 发明授权

US6044013A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6044013A
公开(公告)日：2000-03-28
申请号：US314446
申请日：1999-05-19
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C7/10 , G11C7/12 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C2211/5621 , G11C2211/5642
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.
摘要翻译：提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

86. 发明授权

US5901152A Three-value data storing semiconductor memory system 失效
标题翻译：三值数据存储半导体存储器系统
公开(公告)号：US5901152A
公开(公告)日：1999-05-04
申请号：US839787
申请日：1997-04-16
申请人： Tomoharu Tanaka , Toru Tanzawa
发明人： Tomoharu Tanaka , Toru Tanzawa
IPC分类号： G06F12/16 , G06F11/10 , G11C11/56 , G11C16/02 , G11C17/00 , G06F11/00
CPC分类号： G06F11/1072 , G11C11/5621 , G11C29/00 , G11C7/1006 , G11C8/00
摘要： A three-value data storing semiconductor memory system, which has a plurality of memory cells capable of storing a three-value data item, comprises a first interface for receiving a plurality of binary data items of a first type, each including 2.sup.m binary data items (m=1, 2, 3, . . . ), from an external device, a control circuit for processing the binary data items of the first type input to the first interface, in units of 3k data items (k=1, 2, 3, ), converting each data unit consisting of 3k data items, to 4k binary data items of a third type, and outputting the binary data items of the third type in units of 2.sup.n binary data items (n=0, 1, 2, 3, . . . ) as binary data items of a second type via a second interface.
摘要翻译：具有能够存储三值数据项的多个存储单元的三值数据存储半导体存储器系统包括用于接收第一类型的多个二进制数据项的第一接口，每个二进制数据项包括2m个二进制数据项（m = 1,2,3，...），用于以3k个数据项（k = 1,2）为单位处理输入到第一接口的第一类型的二进制数据项的控制电路，3）将由3k数据项组成的每个数据单元转换为第四类型的4k个二进制数据项，并以2n个二进制数据项（n = 0,1,2）为单位输出第三类型的二进制数据项，3，...）作为第二类型的二进制数据项。

87. 发明授权

US5828621A Semiconductor memory device and high-voltage switching circuit 失效
公开(公告)号：US5828621A
公开(公告)日：1998-10-27
申请号：US941370
申请日：1997-09-30
申请人： Toru Tanzawa , Tomoharu Tanaka , Ken Takeuchi
发明人： Toru Tanzawa , Tomoharu Tanaka , Ken Takeuchi
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C29/00 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C16/12 , G11C16/16 , G11C16/30 , G11C29/50 , G11C29/50004 , G11C29/83 , G11C16/04 , G11C2029/5004
摘要： A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.

88. 发明授权

US5719888A Memory system 失效
公开(公告)号：US5719888A
公开(公告)日：1998-02-17
申请号：US786142
申请日：1997-01-21
申请人： Toru Tanzawa , Tomoharu Tanaka
发明人： Toru Tanzawa , Tomoharu Tanaka
IPC分类号： G06F11/10 , G06F12/16 , G11C11/56 , G11C16/02 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/42 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： G06F11/1072 , G11C11/56 , G11C11/5621 , G11C16/0483 , G11C2211/5641 , G11C29/00
摘要： According to the present invention, a memory system comprises storing section having a plurality of memory elements each of which stores one of n-value storage states corresponding to data "0", "1", . . . , "n-1", and including a plurality of information memory elements for storing n-value information data and a plurality of check memory elements for storing check data, converting section for respectively converting the information data and the check data stored in the memory elements into binary codes having a plurality of bits each constituted by 0 or 1, the binary codes corresponding to the information data and the check data, and detecting/correcting section for detecting and correcting an error on the basis of the binary codes corresponding to the check data and the information data.

89. 发明授权

US5708606A Semiconductor memory device and high-voltage switching circuit 失效
公开(公告)号：US5708606A
公开(公告)日：1998-01-13
申请号：US773893
申请日：1997-01-17
申请人： Toru Tanzawa , Tomoharu Tanaka , Ken Takeuchi
发明人： Toru Tanzawa , Tomoharu Tanaka , Ken Takeuchi
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C29/00 , G11C29/50 , G11C16/00
CPC分类号： G11C29/028 , G11C16/12 , G11C16/16 , G11C16/30 , G11C29/50 , G11C29/50004 , G11C29/83 , G11C16/04 , G11C2029/5004
摘要： A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V.

90. 发明授权

US09053043B2 Method of error correction of a memory 有权
标题翻译：存储器的纠错方法
公开(公告)号：US09053043B2
公开(公告)日：2015-06-09
申请号：US13708222
申请日：2012-12-07
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： G06F11/10 , G11C7/10 , G11C16/04 , G11C16/10 , G11C29/04
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式