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1. 发明授权

US07509566B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07509566B2
公开(公告)日：2009-03-24
申请号：US11747225
申请日：2007-05-10
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： H03M13/00 , G11C29/00 , G11C11/34
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

2. 发明授权

US07908529B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07908529B2
公开(公告)日：2011-03-15
申请号：US12371659
申请日：2009-02-16
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： G11C29/00 , G11C16/04 , H03M13/00
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

3. 发明授权

US09053043B2 Method of error correction of a memory 有权
标题翻译：存储器的纠错方法
公开(公告)号：US09053043B2
公开(公告)日：2015-06-09
申请号：US13708222
申请日：2012-12-07
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： G06F11/10 , G11C7/10 , G11C16/04 , G11C16/10 , G11C29/04
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

4. 发明授权

US08365025B2 Flash memory 有权
公开(公告)号：US08365025B2
公开(公告)日：2013-01-29
申请号：US13046333
申请日：2011-03-11
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： G11C29/00 , G11C16/04
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

5. 发明授权

US07219285B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07219285B2
公开(公告)日：2007-05-15
申请号：US10601636
申请日：2003-06-24
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： G01R31/28 , G06F11/00 , G11C29/00
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

6. 发明授权

US06611938B1 Flash memory 有权
标题翻译：闪存
公开(公告)号：US06611938B1
公开(公告)日：2003-08-26
申请号：US09604692
申请日：2000-06-27
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： H03M1300
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory comprises a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write means. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. With this configuration, processing to generate the check data for the error correction with the internal error correction circuit and processing to input the check data to the write circuit, etc. can be automatically performed in the flash memory even in the period when the external control signal is not input.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路多个数据存储电路和写入装置。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。利用这种配置，即使在外部控制的时间段中也可以在闪速存储器中自动执行利用内部纠错电路生成用于纠错的校验数据的处理和将写入电路等的校验数据输入的处理信号未输入。

7. 发明授权

US07535762B2 Semiconductor memory device 有权
公开(公告)号：US07535762B2
公开(公告)日：2009-05-19
申请号：US12046745
申请日：2008-03-12
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5642
摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

8. 发明授权

US06344996B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06344996B2
公开(公告)日：2002-02-05
申请号：US09768588
申请日：2001-01-25
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5642
摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

9. 发明授权

US06208573B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06208573B1
公开(公告)日：2001-03-27
申请号：US09504903
申请日：2000-02-16
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
IPC分类号： G11C700
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5642
摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

10. 发明授权

US6084799A Nonvolatile semiconductor memory having improved source line drive circuit 失效
标题翻译：具有改进的源极线驱动电路的非易失性半导体存储器
公开(公告)号：US6084799A
公开(公告)日：2000-07-04
申请号：US976492
申请日：1997-11-24
申请人： Toru Tanzawa , Tomoharu Tanaka
发明人： Toru Tanzawa , Tomoharu Tanaka
IPC分类号： G11C16/06 , G11C16/24 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C16/24
摘要： A nonvolatile semiconductor memory, having an improved source line drive circuit, comprises a memory core section including a memory cell array, a control circuit, the memory cell array having a plurality of memory cells respectively, constituted by transistors of layered gate structure having source electrodes, and each of the memory cells being connected to a common word line and a corresponding signal line. The control circuit senses a signal line voltage in accordance with data of the corresponding memory cell, and amplifies the signal line voltage to output a signal. The source electrodes of the plurality of the memory cells are connected to the source diffusion layer in common. A peripheral circuit includes a source line drive circuit for controlling a potential of each source line to be maintained substantially constant.
摘要翻译：具有改进的源极线驱动电路的非易失性半导体存储器包括存储器芯部分，其包括存储单元阵列，控制电路，具有多个存储器单元的存储单元阵列，分别由具有源电极的分层栅极结构的晶体管构成，并且每个存储单元连接到公共字线和对应的信号线。控制电路根据对应的存储单元的数据来感测信号线电压，并且放大信号线电压以输出信号。多个存储单元的源电极共同地连接到源极扩散层。外围电路包括用于控制每条源极线的电位保持基本恒定的源极线驱动电路。

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