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81. 发明授权

US06829134B2 Laminated ceramic electronic component and method for manufacturing the same 有权
公开(公告)号：US06829134B2
公开(公告)日：2004-12-07
申请号：US10615009
申请日：2003-07-08
申请人： Makoto Yamauchi , Akihiro Shimizu , Kazuaki Kawabata , Hiroaki Taira , Hiroyuki Matsumoto
发明人： Makoto Yamauchi , Akihiro Shimizu , Kazuaki Kawabata , Hiroaki Taira , Hiroyuki Matsumoto
IPC分类号： H01G4005
CPC分类号： H01G4/012 , H01G4/232 , H01G4/30
摘要： A highly reliable monolithic ceramic capacitor which has no structural defect, e.g. peeling, and which is not susceptible to water from the outside and a method for manufacturing the same are provided. A lead portion of an internal electrode is configured to have a shape provided with a taper-shaped portion in which the width gradually decreases with increasing proximity to the end surface of a ceramic element, and the shape of the end portion opposite to the lead portion of the internal electrode is adjusted to be substantially rectangular. Regarding a pair of internal electrodes facing each other with the ceramic layer therebetween, the internal electrodes are laminated while the positions thereof are displaced with respect to each other in order that a corner portion in the substantially rectangular portion of one internal electrode are located in the vicinity of, but outside the taper-shaped portion of the other internal electrode.

82. 发明授权

US06809399B2 Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06809399B2
公开(公告)日：2004-10-26
申请号：US10304045
申请日：2002-11-26
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L218234
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储器单元的驱动MISFET，传输MISFET和负载MISFET的栅电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外，通过在第一导电层上叠置局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

83. 发明授权

US06777279B2 Semiconductor integrated circuit device and manufacturing method thereof 失效
公开(公告)号：US06777279B2
公开(公告)日：2004-08-17
申请号：US10412230
申请日：2003-04-14
申请人： Chiemi Hashimoto , Yasuhiko Kawashima , Keizo Kawakita , Masahiro Moniwa , Hiroyasu Ishizuka , Akihiro Shimizu
发明人： Chiemi Hashimoto , Yasuhiko Kawashima , Keizo Kawakita , Masahiro Moniwa , Hiroyasu Ishizuka , Akihiro Shimizu
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10814 , H01L27/10873 , H01L28/91
摘要： Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode. Meanwhile, since the gate electrode in the peripheral circuit region has a gate length longer than that of the gate electrode in the memory array region, the thickness of the gate insulating film just below the center thereof is almost equal to that before the re-oxidation process.

84. 发明授权

US06548885B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06548885B2
公开(公告)日：2003-04-15
申请号：US09755184
申请日：2001-01-08
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L2900
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置来形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

85. 发明授权

US5946565A Semiconductor integrated circuit device and process for manufacturing the same 失效
公开(公告)号：US5946565A
公开(公告)日：1999-08-31
申请号：US880736
申请日：1997-06-23
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： G11C11/412 , H01L21/768 , H01L21/8244 , H01L27/11 , H01L21/8234
CPC分类号： H01L27/11 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , G11C11/412 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

86. 发明授权

US5455438A Semiconductor integrated circuit device in which kink current disturbances of MOS transistors are suppressed 失效
标题翻译：其中抑制了MOS晶体管的扭矩电流干扰的半导体集成电路器件
公开(公告)号：US5455438A
公开(公告)日：1995-10-03
申请号：US69572
申请日：1993-06-01
申请人： Naotaka Hashimoto , Toshiaki Yamanaka , Takashi Hashimoto , Akihiro Shimizu , Nagatoshi Ohki , Hiroshi Ishida
发明人： Naotaka Hashimoto , Toshiaki Yamanaka , Takashi Hashimoto , Akihiro Shimizu , Nagatoshi Ohki , Hiroshi Ishida
IPC分类号： H01L21/762 , H01L27/105 , H01L27/088
CPC分类号： H01L21/76237 , H01L27/105 , Y10S257/903
摘要： Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate. Further, the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the environmental device area is larger than the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the memory cell area.
摘要翻译：公开了一种具有多个精细存储器件及其制造方法的半导体集成电路器件，特别涉及能够抑制MOS晶体管的扭结电流干扰而不降低扩散层的结特性的半导体集成电路器件及其制造方法。在该装置中，形成在环境装置区域即外围电路区域的场氧化物的每个边缘的下表面与半导体衬底的主表面之间的角度小于每个边缘的下表面之间的角度形成在存储单元区域中的场氧化物和半导体衬底的主表面。此外，环境装置区域中的场氧化物的每个边缘在平行于半导体基板的主表面的方向上的延伸大于在平行于主体表面的方向上的延伸半导体衬底，在存储单元区域中的场氧化物的每个边缘。

87. 发明授权

US5354344A Gasoline fuel composition containing 3-butyn-2-one 失效
标题翻译：含有3-丁炔-2-酮的汽油燃料组合物
公开(公告)号：US5354344A
公开(公告)日：1994-10-11
申请号：US921695
申请日：1992-07-30
申请人： Haruo Takizawa , Akihiro Shimizu , Shigehisa Yamada , Hiromichi Ikebe , Hiroaki Hara
发明人： Haruo Takizawa , Akihiro Shimizu , Shigehisa Yamada , Hiromichi Ikebe , Hiroaki Hara
IPC分类号： C10L1/06 , C10L1/02 , C10L1/18 , C10L1/182 , C10L1/185 , G01N33/22
CPC分类号： C10L10/10 , C10L1/023 , C10L1/1824 , C10L1/1852 , C10L1/1855 , C10L1/1857
摘要： A fuel oil composition for use in a spark ignition engine, which comprises conventional gasoline for spark ignition engine use and a compound selected from the group consisting of an alkynyl alcohol, alkynyl ether, alkynyl ketone, alkenyl aldehyde or an acetal thereof, furan or a furan compound, and an alkenyl ether. The gasoline composition for fuel use renders possible improvement of flame propagation speed over a broad range of fuel/air ratios, easy optimization of the ignition timing of a spark ignition engine, improvement of engine output power independently of operation conditions, improvement of ignitability without using metal components when a spark ignition engine is operated with a lean or rich fuel-air mixture, and reduction of cycle fluctuation caused by the variation in the formation of fuel-air mixture which occurs even at the time of normal operation, thereby repressing fluctuations in indicated mean effective pressure, maximum cylinder pressure and the like independently of changes in the fuel/air ratio.
摘要翻译：用于火花点火发动机的燃料油组合物，其包含用于火花点火发动机的常规汽油和选自炔基醇，炔基醚，炔基酮，烯基醛或其缩醛的化合物，呋喃或呋喃化合物和烯基醚。用于燃料使用的汽油组合物可以在广泛的燃料/空气比范围内改善火焰传播速度，容易优化火花点火发动机的点火正时，独立于操作条件改善发动机输出功率，不使用可燃性提高当火花点火发动机以稀薄或丰富的燃料 - 空气混合物操作时，金属部件和即使在正常运行时也发生的燃料 - 空气混合物的形成变化引起的循环波动减少，从而压制波动独立于燃料/空气比的变化表示平均有效压力，最大气缸压力等。

88. 发明授权

US5127470A Apparatus for heat recovery and method for operating the apparatus 失效
标题翻译：用于热回收的装置和操作装置的方法
公开(公告)号：US5127470A
公开(公告)日：1992-07-07
申请号：US565683
申请日：1990-08-09
申请人： Yoshiaki Inaba , Kenji Tokunaga , Akihiro Shimizu , Tetsuzo Kuribayashi
发明人： Yoshiaki Inaba , Kenji Tokunaga , Akihiro Shimizu , Tetsuzo Kuribayashi
IPC分类号： F02C6/18 , F01K3/00 , F01K23/10 , F02G5/02 , F24V30/00 , F28D20/00
CPC分类号： F01K23/10 , F01K3/00 , F28D20/003 , Y02E60/142 , Y10S165/909
摘要： An apparatus for heat recovery from an exhaust gas with waste heat from a heat machinery unit, which comprises a pair of first and second chemical heat-storing units, each comprising a vessel containing a reactant material capable of releasing a reaction-susceptible material upon heating with an exhaust gas and emitting the heat of reaction upon combination with the reaction-susceptible material and a heat exchanger piping provided in the vessel and through which a heat transfer medium is passed. The high temperature gas from the heat machinery unit is applied to the vessel in one of the first and second chemical heat-storing units, thereby resulting in a reaction for leasing the reaction-susceptible material. A further reaction to combine the heat-susceptible material in the vessel in the other of the first or second chemical heat-storing units, and is passed the heat transfer medium through the heat exchanger piping in the vessel in the other of the first or second chemical heat-storing unit for continuously providing a high heat recovery efficiency.
摘要翻译：一种用于从具有来自热机械单元的废热排出的废气进行热回收的装置，其包括一对第一和第二化学储热单元，每个第一和第二化学储热单元包括容纳含有能够在加热时释放反应敏感材料的反应物料的容器与废气结合并且与反应敏感材料组合并发出反应热，以及设置在容器中的热交换器管道，并且传热介质通过该热交换器管道。来自热机械单元的高温气体被施加到第一和第二化学储热单元之一中的容器中，从而导致用于租赁反应敏感材料的反应。在第一或第二化学储热单元中的另一个中将容器中的热敏材料组合的另一反应，并且使传热介质通过容器中的热交换器管道中的第一或第二化学蓄热单元中的另一个化学蓄热单元，用于连续提供高热回收效率。

89. 发明授权

US4850019A Data randomization equipment 失效
标题翻译：数据随机化设备
公开(公告)号：US4850019A
公开(公告)日：1989-07-18
申请号：US926043
申请日：1986-11-03
申请人： Akihiro Shimizu , Shoji Miyaguchi
发明人： Akihiro Shimizu , Shoji Miyaguchi
IPC分类号： H04L9/06
CPC分类号： H04L9/0625 , H04L2209/08 , H04L2209/125
摘要： Input data is split by a splitting part into a plurality of block data having an equal data length to be processed through respective channels. Each channel data is subjected in a function operation part to a function operation in direct or indirect relation to all the other channel data to produce new channel data. Each channel data is subjected in a transform operation part to a transform operation to produce new channel data. All final channel data obtained after function and transform operations are combined by a combining part to obtain randomized data.
摘要翻译：输入数据由分割部分分割为具有相同数据长度的多个块数据，以通过相应的通道进行处理。每个信道数据在功能操作部分中进行与所有其他信道数据的直接或间接关系的功能操作，以产生新的信道数据。每个通道数据在变换操作部分进行变换操作以产生新的通道数据。在功能和变换操作之后获得的所有最终通道数据由组合部分组合以获得随机数据。

90. 发明授权

US09353689B2 Fuel supply device of gas turbine engine 有权
标题翻译：燃气轮机发动机燃油供应装置
公开(公告)号：US09353689B2
公开(公告)日：2016-05-31
申请号：US13637324
申请日：2011-03-23
申请人： Hideki Ogata , Kazuhiko Ohyama , Tomoyuki Hatano , Akihiro Shimizu , Touya Miwa
发明人： Hideki Ogata , Kazuhiko Ohyama , Tomoyuki Hatano , Akihiro Shimizu , Touya Miwa
IPC分类号： F16K11/14 , F02C7/228 , F16K11/044 , F16K31/10 , F16K31/528 , F23K5/04 , F23K5/06 , F23K5/14 , F23R3/34
CPC分类号： F02C7/228 , F05D2220/323 , F05D2240/35 , F05D2270/3015 , F16K11/044 , F16K31/10 , F16K31/528 , F23K5/04 , F23K5/06 , F23K5/147 , F23R3/343 , Y02T50/672
摘要： In a fuel supply device of a gas turbine engine of the present invention, a fuel divider 66 includes a fuel entrance E1 into which the fuel supplied from a collecting fuel passage 63 is introduced; a pilot port 76 connected to the pilot fuel passage 64; a main port 77 connected to the main fuel passage 65; a pilot port needle valve element 101 which adjusts an opening degree of the pilot port 76; a main port needle valve element 102 which opens and closes the main port 77; and a drive element 100 which is actuated according to the fuel pressure at the fuel inlet E1 to drive the pilot port needle valve element 101 and the main port needle valve element 102.
摘要翻译：在本发明的燃气涡轮发动机的燃料供给装置中，燃料分配器66包括从集合燃料通路63供给的燃料被引入的燃料入口E1，连接到先导燃料通道64的先导口76; 连接到主燃料通道65的主端口77; 调节先导口76的开度的先导口针阀元件101; 主端口针阀元件102，其打开和关闭主端口77; 驱动元件100，其根据燃料入口E1处的燃料压力而被驱动，以驱动先导端口针阀元件101和主端口针阀元件102。

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