专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5455438A Semiconductor integrated circuit device in which kink current disturbances of MOS transistors are suppressed 失效
标题翻译：其中抑制了MOS晶体管的扭矩电流干扰的半导体集成电路器件
公开(公告)号：US5455438A
公开(公告)日：1995-10-03
申请号：US69572
申请日：1993-06-01
申请人： Naotaka Hashimoto , Toshiaki Yamanaka , Takashi Hashimoto , Akihiro Shimizu , Nagatoshi Ohki , Hiroshi Ishida
发明人： Naotaka Hashimoto , Toshiaki Yamanaka , Takashi Hashimoto , Akihiro Shimizu , Nagatoshi Ohki , Hiroshi Ishida
IPC分类号： H01L21/762 , H01L27/105 , H01L27/088
CPC分类号： H01L21/76237 , H01L27/105 , Y10S257/903
摘要： Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate. Further, the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the environmental device area is larger than the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the memory cell area.
摘要翻译：公开了一种具有多个精细存储器件及其制造方法的半导体集成电路器件，特别涉及能够抑制MOS晶体管的扭结电流干扰而不降低扩散层的结特性的半导体集成电路器件及其制造方法。在该装置中，形成在环境装置区域即外围电路区域的场氧化物的每个边缘的下表面与半导体衬底的主表面之间的角度小于每个边缘的下表面之间的角度形成在存储单元区域中的场氧化物和半导体衬底的主表面。此外，环境装置区域中的场氧化物的每个边缘在平行于半导体基板的主表面的方向上的延伸大于在平行于主体表面的方向上的延伸半导体衬底，在存储单元区域中的场氧化物的每个边缘。

2. 发明授权

US5296729A Semiconductor memory device having static random access memory 失效
标题翻译：具有静态随机存取存储器的半导体存储器件
公开(公告)号：US5296729A
公开(公告)日：1994-03-22
申请号：US782623
申请日：1991-10-25
申请人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
发明人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
IPC分类号： G03F1/29 , G03F1/30 , G03F1/68 , H01L21/027 , H01L21/8244 , H01L27/11 , H01L27/02 , H01L29/00 , H01L29/78
CPC分类号： H01L27/1108 , Y10S257/903
摘要： There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.
摘要翻译：提供了一种能够通过扩大连接到存储单元的标准电位电源的单元中的电极的有效面积来减小电极电阻的技术。还提供了一种能够通过减小用于标准电位电极的电极中的电极与相邻的其它电极之间分离所需的面积来减小存储单元面积的技术。提供了第一导电类型的两个传输MOS晶体管和两个驱动器MOS晶体管。用于将驱动器MOS晶体管的源极电位固定为标准电位的导电层设置在传输和驱动器MOS晶体管之上，以完全覆盖存储器单元。通过使用具有设置在相同透射部分内的光学透明基板的光掩模进行分离，其具有多个所谓的移相器区域的图案，用于反转透射相位的相位。

3. 发明授权

US5132771A Semiconductor memory device having flip-flop circuits 失效
标题翻译：具有触发电路的半导体存储器件
公开(公告)号：US5132771A
公开(公告)日：1992-07-21
申请号：US503928
申请日：1990-04-04
申请人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
发明人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.
摘要翻译：提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以彼此平行。

4. 发明授权

US5134581A Highly stable semiconductor memory with a small memory cell area 失效
标题翻译：高度稳定的半导体存储器具有小的存储单元面积
公开(公告)号：US5134581A
公开(公告)日：1992-07-28
申请号：US604469
申请日：1990-10-29
申请人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
发明人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
IPC分类号： G11C11/412 , G11C11/419 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , G11C11/419 , H01L27/1108
摘要： In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)
摘要翻译：为了获得具有小单元区域的高度稳定的SRAM单元，单元比率R被设置为R =（WDEFF / LDEFF）/（WTEFF / LTEFF）<3，其中LDEFF和WDEFF表示有效信道长度，并且有效沟道宽度分别为两个驱动MOSFET 3和4，LTEFF和WTEFF分别表示两个传输MOSFET 5和6的有效沟道长度和有效沟道宽度。此外，流入有源负载MOSFET 1和2的最大电流IR被设置为大于当跨栅极施加阈值电压时流入驱动器MOSFET 5的电流IL（1×10 -8 A），并且 MOSFET 5.一对有源负载MOSFET 1和2堆叠在驱动器MOSFET 3和4以及传输MOSFET 5和6上。

5. 发明授权

US5619055A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5619055A
公开(公告)日：1997-04-08
申请号：US429882
申请日：1995-04-27
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加存储单元存储节点被实现，从而减少软错误的发生。通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。

6. 发明授权

US5646423A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5646423A
公开(公告)日：1997-07-08
申请号：US470451
申请日：1995-06-06
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/04 , H01L31/036
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.
摘要翻译：公开了SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFETS之上。存储单元的每个负载MISFET由形成在同一多晶硅膜内的源极，漏极和沟道区域以及由与驱动MISFET不同的导电膜构成的栅电极组成。在具有这种堆叠布置的存储单元中，其每个负载MISFET的源极（漏极）区域和栅电极被图案化以具有彼此重叠的关系，从而增加与每个存储单元存储节点相关联的有效电容。驱动和负载MISFET两者的栅电极分别由n型和p型多晶硅膜形成，并且第一和第二p沟道负载MISFET的漏极区域电连接到第一和第二n沟道驱动MISFET分别通过单独的多晶硅膜。此外，第一和第二负载MISFET的多晶硅栅电极分别电连接到SRAM的每个存储单元中的第二和第一驱动MISFET的漏极区。

7. 发明授权

US5700705A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5700705A
公开(公告)日：1997-12-23
申请号：US470452
申请日：1995-06-06
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. Also, there are formed electrical connections between the polycrystalline silicon gate electrodes of the first and second load MISFETs with that of drain regions of the second and first drive MISFETs, through the poly-Si gate electrodes of the first and second drive MISFETs, in each memory cell of the SRAM, respectively, furthermore.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元的制造，其中负载MISFET堆叠在半导体衬底上方和驱动MISFET上方。每个负载MISFET的制造包括在同一多晶硅膜内形成源极，漏极和沟道区域，以及由不同层导电膜（例如多晶膜）组成的栅电极，而不是驱动MISFET。具有这种堆叠布置的存储单元的制造有助于其每个负载MISFET的源极（漏极）区域和栅极电极的图案化，以使得彼此之间具有重叠关系，从而增加与每个负载MISFET相关联的有效电容存储单元存储节点。驱动和负载MISFET的栅电极分别由n型或n型和p型多晶硅膜形成，并且在第一和第二p沟道负载MISFET的漏极区之间形成电连接与第一和第二n沟道驱动MISFET的漏极区分别通过分离的多晶硅膜。此外，通过第一和第二驱动MISFET的多晶硅栅电极，在第一和第二负载MISFET的多晶硅栅电极与第二和第一驱动MISFET的漏极区域之间形成电连接此外，SRAM的存储单元分别。

8. 发明授权

US5298764A Semiconductor memory device having a field effect transistor with a channel formed from a polycrystalline silicon film 失效
标题翻译：具有具有由多晶硅膜形成的沟道的场效应晶体管的半导体存储器件
公开(公告)号：US5298764A
公开(公告)日：1994-03-29
申请号：US846892
申请日：1992-03-06
申请人： Toshiaki Yamanaka , Takashi Hashimoto , Naotaka Hashimoto
发明人： Toshiaki Yamanaka , Takashi Hashimoto , Naotaka Hashimoto
IPC分类号： H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78696 , H01L27/0922 , H01L27/1108 , H01L29/78609 , Y10S257/903
摘要： In a semiconductor device and, in particular, a semiconductor memory device in which a channel region formed in a polycrystalline film of a first channel conductivity type insulated gate field effect transistor is divided into a first channel region, which is in contact with a drain region, and a second channel region and the second channel region contains a second conductivity type impurity or a first conductivity type impurity whose density is higher than the impurity density of the first channel region, the threshold voltage can be controlled and the leakage current can be made small.
摘要翻译：在半导体器件中，特别是半导体存储器件，其中形成在第一沟道导电型绝缘栅场效应晶体管的多晶膜中的沟道区被分成与漏区接触的第一沟道区并且第二沟道区域和第二沟道区域包含密度高于第一沟道区的杂质浓度的第二导电型杂质或第一导电型杂质，可以控制阈值电压并且可以使漏电流小。

9. 发明授权

US5194749A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5194749A
公开(公告)日：1993-03-16
申请号：US837689
申请日：1992-02-19
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.
摘要翻译：在CMOS型SRAM的存储单元中，具有作为源极，漏极和沟道区域的多晶硅膜的负载MISFET堆叠在驱动MISFET上，驱动MISFET和负载MISFET的栅电极由不同层中的导电膜构成。设置在多晶硅膜上的源极和漏极的面积与负载MISFET的栅电极重叠。

10. 发明授权

US5483083A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5483083A
公开(公告)日：1996-01-09
申请号：US028128
申请日：1993-03-09
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.
摘要翻译：提供采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET上方。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由与驱动MISFET的不同层导电膜组成的栅电极组成。在用于将地电位施加到其驱动MISFET的源极区的存储单元的驱动和负载MISFET的堆叠布置中，形成作为单独导电层的布线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式