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81. 发明授权

US5761122A Semiconductor memory device with program/erase verification 失效
标题翻译：具有编程/擦除验证的半导体存储器件
公开(公告)号：US5761122A
公开(公告)日：1998-06-02
申请号：US749673
申请日：1996-11-15
申请人： Hiroshi Nakamura , Junichi Miyamoto , Yoshihisa Iwata , Keniti Imamiya
发明人： Hiroshi Nakamura , Junichi Miyamoto , Yoshihisa Iwata , Keniti Imamiya
IPC分类号： G11C16/06 , G11C7/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115
CPC分类号： G11C16/3477 , G11C16/10 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3486 , G11C7/00
摘要： A semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each, of which is arranged at one end of at least one bit line connected to the memory cell array and for latching programming data, a control section for judging whether all of a plurality of latched data included in date latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, a section for detecting potentials of the plurality of the first nodes and for judging whether all data latched by the latch circuits are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and a section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, are the same as the first data or not.
摘要翻译：半导体存储器件包括半导体衬底，具有存储单元的存储单元阵列，每个存储单元存储矩阵形成在半导体衬底上的数据，多个数据锁存电路，每个数据锁存电路至少布置在一端连接到存储单元阵列的一位线和用于锁存编程数据的控制部分，用于判断包括在由多个数据锁存电路构成的日期锁存组中的多个锁存数据是否与第一数据相同的控制部分并且用于根据判断结果控制多个第一节点的电位变化，用于检测多个第一节点的电位的部分和用于判断由锁存电路锁存的所有数据是否与第一数据相同，用于根据判断结果控制多个第二节点的电位，以及用于检测多个第二节点和fo的电位的部分 r输出由数据锁存电路锁存的所有数据是否与第一数据相同的判断结果。

82. 发明授权

US5734286A Driving device of charge pump circuit and driving pulse generation method thereof 失效
标题翻译：电荷泵电路的驱动装置及其驱动脉冲产生方法
公开(公告)号：US5734286A
公开(公告)日：1998-03-31
申请号：US245770
申请日：1994-05-18
申请人： Yasuhisa Takeyama , Junichi Miyamoto , Yoshihisa Iwata , Hironori Banba , Hideko Oodaira
发明人： Yasuhisa Takeyama , Junichi Miyamoto , Yoshihisa Iwata , Hironori Banba , Hideko Oodaira
IPC分类号： G11C11/407 , H02M3/07 , H03K5/15 , H03K5/151 , H03K5/156 , G05F1/46
CPC分类号： H02M3/073 , H03K5/15013 , H03K5/1515 , H03K5/1565
摘要： A semiconductor circuit device includes an oscillator for outputting an oscillating signal, a driving signal generator for generating driving signals having respective phases based on a counting of oscillations of the oscillating signal, and a charge pump circuit driven by the driving signals. A pulse width ratio of the driving signals to one another is constant even when an oscillation period of the oscillating signal output by the oscillator changes, whereby the charge pump operates properly under changing conditions.
摘要翻译：半导体电路装置包括用于输出振荡信号的振荡器，用于产生基于对振荡信号的振荡的计数的各相的驱动信号的驱动信号发生器和由驱动信号驱动的电荷泵电路。即使当由振荡器输出的振荡信号的振荡周期改变时，驱动信号的脉冲宽度比也是恒定的，从而在变化的条件下电荷泵正常工作。

83. 发明授权

US5637895A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5637895A
公开(公告)日：1997-06-10
申请号：US523315
申请日：1995-09-05
申请人： Yoshihisa Iwata , Hiroshi Nakamura
发明人： Yoshihisa Iwata , Hiroshi Nakamura
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0483
摘要： In a non-volatile semiconductor memory device having a memory cell array formed by arranging a plurality of non-volatile reloadable semiconductor memory cells (Mi) and select gate elements on a semiconductor substrate (11) via a gate insulating film (13), each memory cell being formed by interposing an interlayer insulating film (15) between a charge storage layer and a control gate line (16.sub.i), the memory device comprises a plurality of select gate lines (14.sub.i) formed by a wiring layer the same as the charge storage layer of the memory cells, as gate electrodes of the select gate elements; and select gate over-adjacent connect lines (16.sub.9, 16.sub.10) formed by a wiring layer the same as the control gate lines (16.sub.i) of the memory cells and located over the select gate lines (14.sub.9, 14.sub.10) via an insulating film in such a way as to be kept floated without contacting with any other wires and potential nodes.
摘要翻译：在通过经由栅极绝缘膜（13）在半导体衬底（11）上布置多个非易失性可重载半导体存储单元（Mi）和选择栅极元件而形成的存储单元阵列的非易失性半导体存储器件中，存储单元通过在电荷存储层和控制栅极线（16i）之间插入层间绝缘膜（15）形成，所述存储器件包括由与所述电荷相同的布线层形成的多个选择栅极线（14i）存储单元的存储层，作为选择栅极元件的栅电极; 并且选择由与存储单元的控制栅极线（16i）相同的布线层形成的并且位于选择栅极线（149,1410）上方的栅极相邻连接线（169,1610），该绝缘膜经由绝缘膜一种在不与任何其他电线和潜在节点接触的情况下保持浮动的方式。

84. 发明授权

US5615165A Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US5615165A
公开(公告)日：1997-03-25
申请号：US576564
申请日：1995-12-21
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

85. 发明授权

US5528547A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
公开(公告)号：US5528547A
公开(公告)日：1996-06-18
申请号：US332391
申请日：1994-10-31
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

86. 发明授权

US5268867A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5268867A
公开(公告)日：1993-12-07
申请号：US957001
申请日：1992-10-06
申请人： Masaki Momodomi , Yasuo Itoh , Yoshihisa Iwata , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Masaki Momodomi , Yasuo Itoh , Yoshihisa Iwata , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/409 , G11C5/14 , G11C7/10 , G11C16/06 , G11C16/20 , G11C16/26 , G11C7/00
CPC分类号： G11C7/1048 , G11C16/20 , G11C16/26 , G11C5/147
摘要： The present invention provides a semiconductor memory device capable of reducing its current consumption, controlling the generation of noise, and increasing in access using a precharge voltage applied to a precharge circuit. In the semiconductor memory device, a precharge circuit is connected to a pair of data input/output lines, and includes a MOS transistor connected between one of the data input/output lines and a node of a precharge voltage and a MOS transistor connected between the other data input/output line and a node of the precharge voltage. The gates of the MOS transistors are supplied with control signals so that the MOS transistors are turned on when the data input/output lines are precharged. A MOS transistor is connected to the data input/output lines for equalizing them. The precharge voltage is set to half of a value obtained by subtracting the threshold voltage of the MOS transistor from the power supply voltage.
摘要翻译：本发明提供一种半导体存储器件，其能够降低其电流消耗，控制噪声的产生，并且使用施加到预充电电路的预充电电压来增加存取。在半导体存储器件中，预充电电路连接到一对数据输入/输出线，并且包括连接在数据输入/输出线之一和预充电电压的节点之间的MOS晶体管和连接在其他数据输入/输出线和预充电电压的节点。 MOS晶体管的栅极被提供控制信号，使得当数据输入/输出线被预充电时MOS晶体管导通。 MOS晶体管连接到数据输入/输出线，以使它们均衡。预充电电压被设定为通过从电源电压减去MOS晶体管的阈值电压而获得的值的一半。

87. 发明授权

US5247480A Electrically erasable progammable read-only memory with nand cell blocks 失效
标题翻译：具有n个单元块的电可擦除可编程只读存储器
公开(公告)号：US5247480A
公开(公告)日：1993-09-21
申请号：US773723
申请日：1991-10-09
申请人： Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Fujio Masuoka
发明人： Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Fujio Masuoka
IPC分类号： G11C16/08 , G11C16/12 , G11C16/30
CPC分类号： G11C16/08 , G11C16/12 , G11C16/30
摘要： An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.
摘要翻译：电可擦除可编程只读存储器具有存储单元块，每个存储单元块分别具有与位线相关联的NAND型单元单元。每个单元单元具有浮置型存储单元晶体管的串联电路和设置在相应位线和存储单元晶体管的串联电路之间的选择晶体管。向存储单元块共同地提供行解码器，用于产生提供给连接到选择晶体管的选择栅极控制线和单元单元中所选择的字线或线的“H”电平电压。为每个存储单元块提供升压电路，用于使“H”电平电压增加到足以使单元晶体管导通的预选电位电平。升压电路包括用于选择栅极控制线的第一升压部分和用于字线的第二部分。第二部分响应于第一部分的输出电压而工作。

88. 发明授权

US4764693A Semiconductor sense circuit suitable for buffer circuit in semiconductor memory chip 失效
标题翻译：半导体感应电路适用于半导体存储芯片中的缓冲电路
公开(公告)号：US4764693A
公开(公告)日：1988-08-16
申请号：US48813
申请日：1987-05-12
申请人： Yoshihisa Iwata
发明人： Yoshihisa Iwata
IPC分类号： G11C11/413 , G11C7/06 , G11C7/10 , G11C8/06 , G11C11/408 , H03K17/04 , H03K3/356 , H03K17/687 , H03K19/01
CPC分类号： G11C7/1057 , G11C7/065 , G11C7/1051 , G11C8/06
摘要： A sense circuit for use in a semiconductor memory senses an input signal by comparing the input signal with a reference voltage. The sense circuit comprises a sense amplifier having first and second nodes, and first and second transfer gates. The first transfer gate couples the input signal to the first node of the sense amplifier. The second transfer gate couples the reference voltage to the second node of the sense amplifier. A level-shift circuit is provided between the second node of the sense amplifier and the second transfer gate. In response to the voltage level of the input signal latched in the first node, the level-shift circuit shifts the level of the reference voltage latched in the second node of the sense amplifier to a lower level when the input signal is high in voltage level, and shifts it to a higher level when the input signal is low in voltage level.
摘要翻译：用于半导体存储器的感测电路通过将输入信号与参考电压进行比较而感测输入信号。感测电路包括具有第一和第二节点的读出放大器以及第一和第二传输门。第一传输门将输入信号耦合到读出放大器的第一节点。第二传输门将参考电压耦合到读出放大器的第二个节点。在读出放大器的第二节点和第二传输门之间提供电平移位电路。响应于在第一节点中锁存的输入信号的电压电平，当输入信号的电压电平高时，电平移位电路将读出放大器的第二节点中锁存的参考电压的电平移位到较低电平，并且当输入信号的电压电平低时，将其移动到更高的电平。

89. 发明授权

US08334551B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08334551B2
公开(公告)日：2012-12-18
申请号：US13120987
申请日：2009-08-25
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
IPC分类号： H01L29/792 , G11C11/34
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n
摘要翻译：每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。对于每个存储块，存储器串按第二方向布置有m列。布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。满足式（1）所示的关系：（式1）m> = n

90. 发明授权

US08203882B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08203882B2
公开(公告)日：2012-06-19
申请号：US12718353
申请日：2010-03-05
申请人： Tomoo Hishida , Yoshihisa Iwata
发明人： Tomoo Hishida , Yoshihisa Iwata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.
摘要翻译：当在一个存储单元块中执行数据擦除操作时，将第一电压施加到从一个存储单元块中的m个源极线中选择的一个源极线。在数据擦除操作开始之前等于源极线的电压的第二电压被施加到其它源极线。然后，在施加第一电压的一定的时间延迟之后，将小于第一电压的第三电压施加到连接到所选择的源极线的源极侧选择晶体管的第三导电层。然后，由于第一和第三电压之间的电位差，在第三栅极绝缘层附近产生空穴电流。将第四电压施加到连接到要擦除的存储晶体管之一的第一导电层之一。其他第一导电层进入浮置状态。

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