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81. 发明申请

US20130313643A1 Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) 有权
标题翻译：用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法
公开(公告)号：US20130313643A1
公开(公告)日：2013-11-28
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
摘要翻译：一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离存在于第二导电装置区域上的高k栅介质层。连接栅极导体形成在高k栅介质层的第一部分和第二部分上。连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。用含氧气氛曝光改变暴露的半导体器件的阈值电压。

82. 发明授权

US08552487B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08552487B2
公开(公告)日：2013-10-08
申请号：US13568601
申请日：2012-08-07
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： A semiconductor structure includes a SOI substrate having a top silicon layer overlying an insulation layer, which overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, which device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlying the doped portion, the backside strap being coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlying the first portion.
摘要翻译：半导体结构包括：SOI衬底，其具有覆盖在底部硅层上的绝缘层的顶部硅层; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，位于掺杂部分下面的背侧带的至少第一部分，背面带在背面带的第一端处耦合到顶部硅层的掺杂部分，并且连接到电容器在背面带的第二端; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，第二外延沉积材料进一步至少部分地覆盖在第一部分上。

83. 发明申请

US20130249002A1 Structure and method to improve etsoi mosfets with back gate 有权
标题翻译：用后门改善等离子体的结构和方法
公开(公告)号：US20130249002A1
公开(公告)日：2013-09-26
申请号：US13424447
申请日：2012-03-20
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/84 , H01L29/66545
摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.
摘要翻译：改进ETSOI MOSFET器件的结构和方法。提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。

84. 发明授权

US08486776B2 Strained devices, methods of manufacture and design structures 有权
标题翻译：应变装置，制造方法和设计结构
公开(公告)号：US08486776B2
公开(公告)日：2013-07-16
申请号：US12886881
申请日：2010-09-21
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
摘要翻译：应变Si和应变SiGe绝缘体器件，制造方法和设计结构。该方法包括在绝缘体上硅晶片上生长SiGe层。该方法还包括将SiGe层图案化成PFET和NFET区域，使得PFET和NFET区域中的SiGe层中的应变被放宽。该方法还包括通过离子注入直接在SiGe层下面的Si层的至少一部分而非晶化。该方法还包括进行热退火以使Si层重结晶，使得晶格常数与弛豫SiGe的晶格常数相匹配，从而在NFET区域上产生拉伸应变。该方法还包括从NFET区域去除SiGe层。该方法还包括执行Ge工艺以将PFET区域中的Si层转换为压缩应变的SiGe。

85. 发明申请

US20130175661A1 Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same 审中-公开
标题翻译：集成电路具有后门控，改进隔离和降低电阻以及制造方法
公开(公告)号：US20130175661A1
公开(公告)日：2013-07-11
申请号：US13623198
申请日：2012-09-20
申请人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF2, B18H22, C16H10, Si, Ge or As as an implant species to amorphize the silicon, and by annealing the amorphized silicon to re-crystallize the amorphized silicon.
摘要翻译：一种结构包括硅衬底; 硅衬底中的至少两个孔; 和分离两口井的深沟槽隔离（DTI）。 DTI具有顶部和底部，其宽度大于顶部的宽度。该结构还包括设置在一个阱中的至少两个半导体器件，其中至少两个半导体器件由浅沟槽隔离（STI）隔开。在DTI的顶部部分和STI的侧壁的结构中，由掺杂的再结晶硅组成。掺杂的再结晶硅可以通过使用例如Xe，In，BF 2，B 18 H 22，C 16 H 10，Si，Ge或As中的一种的成角度的离子注入来形成，以使硅非晶化，并且通过退火非晶化硅使非晶化硅再结晶。

86. 发明申请

US20130175579A1 TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN 审中-公开
标题翻译：带有通道和放大源/漏极的晶体管
公开(公告)号：US20130175579A1
公开(公告)日：2013-07-11
申请号：US13347161
申请日：2012-01-10
申请人： Kangguo Cheng , Ali Khakifirooz , Sivananda Kanakasabapathy , Pranita Kulkarni , Balasubramanian S. Haran
发明人： Kangguo Cheng , Ali Khakifirooz , Sivananda Kanakasabapathy , Pranita Kulkarni , Balasubramanian S. Haran
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.
摘要翻译：晶体管包括第一半导体层。第二半导体层位于第一半导体层上。去除第二半导体层的一部分以暴露第一半导体层的第一部分并提供第二半导体层的垂直侧壁。栅极间隔物位于第二半导体层上。栅极电介质包括位于第一半导体层的第一部分上的第一部分和与第二半导体层的垂直侧壁相邻的第二部分。栅极导体位于栅极电介质的第一部分上并邻接栅极电介质第二部分。沟道区位于第一半导体层的第一部分的至少一部分中。上升的源极/漏极区域位于第二半导体层中。凸起的源极/漏极区域的至少一部分位于栅极间隔物的下方。

87. 发明授权

US08450807B2 MOSFETs with reduced contact resistance 有权
标题翻译：具有降低的接触电阻的MOSFET
公开(公告)号：US08450807B2
公开(公告)日：2013-05-28
申请号：US12719934
申请日：2010-03-09
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/70
CPC分类号： H01L29/66477 , H01L21/28518 , H01L23/485 , H01L29/0847 , H01L29/165 , H01L29/41725 , H01L29/41766 , H01L29/41783 , H01L29/45 , H01L29/456 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.
摘要翻译：提供了形成具有降低的接触电阻的场效应晶体管的方法和结构。降低的接触电阻由金属半导体合金接触电阻降低和导电填充通孔接触 - 金属半导体合金接触电阻表现出来。在本公开内容中通过纹理化晶体管的源极区域和/或晶体管的漏极区域的表面来实现降低的接触电阻。通常，在本公开内容中，源极区域和漏极区域都被纹理化。与包括平坦源极区域和/或平坦漏极区域的常规晶体管相比，纹理化源极区域和/或织构化漏极区域具有增加的面积。在源极区域的纹理表面和/或漏极区域的纹理化表面上形成金属半导体合金，例如硅化物。在金属半导体合金的顶部形成导电填充的通孔接触。

88. 发明授权

US08445345B2 CMOS structure having multiple threshold voltage devices 失效
标题翻译： CMOS结构具有多个阈值电压器件
公开(公告)号：US08445345B2
公开(公告)日：2013-05-21
申请号：US13227750
申请日：2011-09-08
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/8238
CPC分类号： H01L29/51 , H01L21/28176 , H01L21/823857 , H01L21/823864 , H01L29/49 , H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7833
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.
摘要翻译：形成具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构的方法包括在半导体衬底上形成第一晶体管器件和第二晶体管器件。第一晶体管器件和第二晶体管器件最初具有牺牲性虚拟栅极结构。去除牺牲虚拟栅极结构，并且为第一晶体管器件选择性地形成一组垂直氧化物间隔物。垂直氧化物间隔物组与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。

89. 发明申请

US20130105818A1 MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION AND METHOD OF FABRICATION 有权
标题翻译：具有半导体通道的MOSFET和具有增强结隔离的嵌入式压电器和制造方法
公开(公告)号：US20130105818A1
公开(公告)日：2013-05-02
申请号：US13283308
申请日：2011-10-27
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
摘要翻译：场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

90. 发明申请

US20130082308A1 SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS 有权
标题翻译：具有扩展扩展的半导体器件
公开(公告)号：US20130082308A1
公开(公告)日：2013-04-04
申请号：US13251757
申请日：2011-10-03
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.
摘要翻译：公开了晶体管器件及其制造方法。在一种方法中，在基板上形成虚拟栅极结构。虚拟门结构的底部是底切的。此外，在基板上形成阶梯状，凸起的源极和漏极区域，以及由底切形成的至少一个底切部。去除虚拟栅极结构并在衬底上形成替换栅极。

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