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81. 发明授权

US07019352B2 Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having ferroelectric components 有权
标题翻译：低硅氢层，用于抑制具有铁电元件的半导体器件中的氢相关退化
公开(公告)号：US07019352B2
公开(公告)日：2006-03-28
申请号：US10635994
申请日：2003-08-07
申请人： K. R. Udayakumar , Martin G. Albrecht , Theodore S. Moise , Scott R. Summerfelt , Sarah I. Hartwig
发明人： K. R. Udayakumar , Martin G. Albrecht , Theodore S. Moise , Scott R. Summerfelt , Sarah I. Hartwig
IPC分类号： H01L27/01
CPC分类号： H01L21/76829 , H01L21/3185 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.
摘要翻译：公开了半导体器件和制造方法，其中提供一个或多个低硅氢SiN栅极以阻止氢扩散到铁电电容器中并进入晶体管栅极电介质界面区域。可以将阻挡层用作在形成强电介质电容器的电平以上和/或以下的半导体器件结构的各种级别的蚀刻停止层，以便降低铁电电容器的开关极化特性的氢相关劣化，并且降低器件晶体管的负偏压温度不稳定性。

82. 发明授权

US06872669B1 PZT (111) texture through Ir texture improvement 有权
标题翻译： PZT（111）纹理通过Ir纹理改进
公开(公告)号：US06872669B1
公开(公告)日：2005-03-29
申请号：US10742190
申请日：2003-12-19
申请人： Scott R. Summerfelt , Sanjeev Aggarwal
发明人： Scott R. Summerfelt , Sanjeev Aggarwal
IPC分类号： H01L21/02 , H01L21/302 , H01L21/314 , H01L21/316 , H01L21/321 , H01L21/3213
CPC分类号： H01L28/55 , H01L21/3145 , H01L21/31691 , H01L21/3212 , H01L21/32131 , H01L28/65 , H01L28/75
摘要： The present invention is directed to a method of forming a ferroelectric capacitor having a (111) PZT texture. The method includes forming a smooth bottom electrode diffusion barrier layer that facilitates a preferential (111) texture in the subsequently formed bottom electrode layer. The (111) bottom electrode layer texture than facilitates a high quality (111) texture in the overlying PZT layer, thereby improving bit-to-bit polarization charge uniformity for various capacitors as the ferroelectric capacitor sizes continue to shrink.
摘要翻译：本发明涉及形成具有（111）PZT纹理的铁电电容器的方法。该方法包括形成平滑的底部电极扩散阻挡层，其有利于随后形成的底部电极层中的优先（111）纹理。（111）底电极层结构有利于上覆PZT层中的高质量（111）纹理，从而提高了随着铁电电容器尺寸的不断缩小，各种电容器的位对齐极化电荷均匀性。

83. 发明授权

US06841396B2 VIA0 etch process for FRAM integration 有权
标题翻译：用于FRAM集成的VIA0蚀刻工艺
公开(公告)号：US06841396B2
公开(公告)日：2005-01-11
申请号：US10440697
申请日：2003-05-19
申请人： Francis Gabriel Celii , K. R. Udayakumar , Scott R. Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , K. R. Udayakumar , Scott R. Summerfelt , Theodore S. Moise
IPC分类号： H01L21/00 , H01L21/20 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.
摘要翻译：铁电存储器件包括逻辑可编程电容参考电路。电路适于在感测操作模式期间产生参考电压，其中参考电压包括作为一个以上存储器条件的函数的值。存储器件还包括位线对，其中位线对的第一位线具有耦合的铁电电容器用于感测位线对，并且位线对的第二位线耦合到参考电压。感测电路耦合到位线对，并且被配置为使用与第一位线相关联的电压和第二位线上的参考电压来检测与铁电电容器相关联的数据状态。

84. 发明授权

US06686236B2 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing 有权
标题翻译：通过金属有机化学气相沉积或其他处理防止PZT形成期间IrOx的还原的方法
公开(公告)号：US06686236B2
公开(公告)日：2004-02-03
申请号：US10036827
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01L218242
CPC分类号： H01L21/02197 , C23C14/08 , H01L21/02271 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/75
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。以上述方式，铁电电容器的耐疲劳性大幅度提高。

85. 发明授权

US06635498B2 Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch 有权
标题翻译：在底部电极蚀刻期间用侧壁构图FeRAM电容器的方法
公开(公告)号：US06635498B2
公开(公告)日：2003-10-21
申请号：US10222718
申请日：2002-08-16
申请人： Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo , Sanjeev Aggarwal , Theodore S. Moise, IV
发明人： Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo , Sanjeev Aggarwal , Theodore S. Moise, IV
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/31122 , H01L21/32136 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。

86. 发明授权

US06548343B1 Method of fabricating a ferroelectric memory cell 有权
标题翻译：制造铁电存储单元的方法
公开(公告)号：US06548343B1
公开(公告)日：2003-04-15
申请号：US09702985
申请日：2000-10-31
申请人： Scott R. Summerfelt , Theodore S. Moise , Guoqiang Xing , Luigi Colombo , Tomoyuki Sakoda , Stephen R. Gilbert , Alvin L. S. Loke , Shawming Ma , Rahim Kavari , Laura Wills-Mirkarimi , Jun Amano
发明人： Scott R. Summerfelt , Theodore S. Moise , Guoqiang Xing , Luigi Colombo , Tomoyuki Sakoda , Stephen R. Gilbert , Alvin L. S. Loke , Shawming Ma , Rahim Kavari , Laura Wills-Mirkarimi , Jun Amano
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.
摘要翻译：本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤形成阻挡层的步骤。

87. 发明授权

US06444542B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06444542B2
公开(公告)日：2002-09-03
申请号：US09826283
申请日：2001-04-03
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L2176
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

88. 发明授权

US06291282B1 Method of forming dual metal gate structures or CMOS devices 有权
标题翻译：形成双金属栅极结构或CMOS器件的方法
公开(公告)号：US06291282B1
公开(公告)日：2001-09-18
申请号：US09500330
申请日：2000-02-08
申请人： Glen D. Wilk , Scott R. Summerfelt
发明人： Glen D. Wilk , Scott R. Summerfelt
IPC分类号： H01L218283
CPC分类号： H01L29/4966 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L29/42376 , H01L29/495 , H01L29/66545 , H01L29/6659
摘要： An embodiment of the instant invention is a method of forming a first transistor having a first gate electrode and a second transistor having a second gate electrode on a semiconductor substrate, the method comprising the steps of: forming a conductive material (step 216 of FIG. 2) insulatively disposed over the semiconductor substrate, the conductive material having a work function; and altering a portion of the conductive material (step 218 of FIG. 2) so as to change the work function of the altered conductive material, the conductive material to form the first gate electrode and the altered conductive material to form the second gate electrode. Preferably, the first transistor is an NMOS device, the second transistor is a PMOS device, and the first transistor and the second transistor form a CMOS device. The conductive material is, preferably, comprised of a conductor selected from the group consisting of: Ta, Mo, Ti and any combination thereof. Preferably, the step of altering a portion of the conductive material is comprised of: subjecting the portion of the conductive material to a plasma which incorporates a nitrogen-containing gas.
摘要翻译：本发明的一个实施例是一种在半导体衬底上形成具有第一栅电极和第二晶体管的第一晶体管的方法，所述第一晶体管具有第二栅电极，所述方法包括以下步骤：形成导电材料（图1的步骤216）。 2）绝缘地设置在半导体衬底上，导电材料具有功函数; 并改变导电材料的一部分（图2的步骤218），以改变改变的导电材料的功函数，导电材料形成第一栅电极和改变的导电材料以形成第二栅电极。优选地，第一晶体管是NMOS器件，第二晶体管是PMOS器件，并且第一晶体管和第二晶体管形成CMOS器件。导电材料优选由选自Ta，Mo，Ti及其任何组合的导体组成。优选地，改变导电材料的一部分的步骤包括：使导电材料的该部分经受含有含氮气体的等离子体。

89. 发明授权

US06275370B1 Electrical connections to dielectric materials 有权
公开(公告)号：US06275370B1
公开(公告)日：2001-08-14
申请号：US09778641
申请日：2001-02-07
申请人： Bruce E. Gnade , Scott R. Summerfelt
发明人： Bruce E. Gnade , Scott R. Summerfelt
IPC分类号： H01G406
摘要： A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g. tantalum pentoxide 40) that are formed are resistive, they are dispersed within the noble metal matrix, leaving a conductive path from the top of the layer to the bottom. This invention provides a stable and electrically conductive electrode for high-dielectric-constant materials while using standard integrated circuit materials to facilitate and economize the manufacturing process.

90. 发明授权

US06215650B1 Electrical connections to dielectric materials 有权
标题翻译：与电介质材料的电气连接
公开(公告)号：US06215650B1
公开(公告)日：2001-04-10
申请号：US09521504
申请日：2000-03-09
申请人： Bruce E. Gnade , Scott R. Summerfelt
发明人： Bruce E. Gnade , Scott R. Summerfelt
IPC分类号： H01G406
CPC分类号： H01L28/75 , H01L21/32051 , H01L28/55 , H01L28/56 , H01L28/60 , Y10S505/818 , Y10T29/435 , Y10T29/49128
摘要： A preferred embodiment of this invention includes an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g. tantalum pentoxide 40) that are formed are resistive, they are dispersed within the noble metal matrix, leaving a conductive path from the top of the layer to the bottom. This invention provides a stable and electrically conductive electrode for high-dielectric-constant materials while using standard integrated circuit materials to facilitate and economize the manufacturing process.
摘要翻译：本发明的优选实施方案包括可氧化层（例如钽48），覆盖可氧化层的氧吸气层（例如铂/钽混合物34），覆盖氧吸气层的贵金属层（例如铂36）和高介电常数材料层（例如钛酸钡锶38）覆盖贵金属层。所提出的新颖结构提供与高介电常数材料的电连接，而不存在电流结构的缺点。氧吸气层控制氧气扩散，使下电极或下电极/衬底界面处的电阻层的形成最小化。吸氧层用作氧的吸除位置，其中氧氧化层的反应性金属部分，使层的贵金属部分保持完整。虽然形成的氧化物/低氧化物（例如五氧化二钽40）是电阻的，但是它们分散在贵金属基质内，留下从层的顶部到底部的导电路径。本发明提供一种用于高介电常数材料的稳定且导电的电极，同时使用标准集成电路材料来促进和节约制造工艺。

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