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1. 发明授权

US07019352B2 Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having ferroelectric components 有权
标题翻译：低硅氢层，用于抑制具有铁电元件的半导体器件中的氢相关退化
公开(公告)号：US07019352B2
公开(公告)日：2006-03-28
申请号：US10635994
申请日：2003-08-07
申请人： K. R. Udayakumar , Martin G. Albrecht , Theodore S. Moise , Scott R. Summerfelt , Sarah I. Hartwig
发明人： K. R. Udayakumar , Martin G. Albrecht , Theodore S. Moise , Scott R. Summerfelt , Sarah I. Hartwig
IPC分类号： H01L27/01
CPC分类号： H01L21/76829 , H01L21/3185 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.
摘要翻译：公开了半导体器件和制造方法，其中提供一个或多个低硅氢SiN栅极以阻止氢扩散到铁电电容器中并进入晶体管栅极电介质界面区域。可以将阻挡层用作在形成强电介质电容器的电平以上和/或以下的半导体器件结构的各种级别的蚀刻停止层，以便降低铁电电容器的开关极化特性的氢相关劣化，并且降低器件晶体管的负偏压温度不稳定性。

2. 发明授权

US06982448B2 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same 有权
标题翻译：铁电电容器氢屏障及其制造方法
公开(公告)号：US06982448B2
公开(公告)日：2006-01-03
申请号：US10803445
申请日：2004-03-18
申请人： K. R. Udayakumar , Theodore S. Moise , Scott R. Summerfelt
发明人： K. R. Udayakumar , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供了氢屏障和制造方法，用于保护铁电电容器（CFE）在半导体器件（102）中的氢扩散，其中氮化的氧化铝（N-AlO x X）为形成在铁电电容器（CFE）上，并且在氮化的氧化铝（N-AlO x N）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（C FE）上形成氧化铝（AlO x N，N-AlO x x），其上形成有氧化铝（AlO x N，N-AlO x）上的两个或更多个氮化硅层（112,117），其中第二氮化硅层（112 ）包括低硅氢SiN材料。

3. 发明授权

US07183602B2 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same 有权
标题翻译：铁电电容器氢屏障及其制造方法
公开(公告)号：US07183602B2
公开(公告)日：2007-02-27
申请号：US11033224
申请日：2005-01-11
申请人： K. R. Udayakumar , Theodore S. Moise , Scott R. Summerfelt
发明人： K. R. Udayakumar , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117）氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

4. 发明授权

US06876021B2 Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier 有权
标题翻译：在电容器侧壁上使用无定形氧化铝作为氢气屏障
公开(公告)号：US06876021B2
公开(公告)日：2005-04-05
申请号：US10303560
申请日：2002-11-25
申请人： J. Scott Martin , Scott R. Summerfelt , Theodore S. Moise , Kelly J. Taylor , Luigi Colombo , Sanjeev Aggarwal , Sirisha Kuchimanchi , K. R. Udayakumar , Lindsey Hall
发明人： J. Scott Martin , Scott R. Summerfelt , Theodore S. Moise , Kelly J. Taylor , Luigi Colombo , Sanjeev Aggarwal , Sirisha Kuchimanchi , K. R. Udayakumar , Lindsey Hall
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L31/119
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.
摘要翻译：本发明形成减轻铁电电容器的氢污染的侧壁扩散阻挡层。本发明的侧壁扩散阻挡层通过物理气相沉积工艺在低温下形成。通过这样做，侧壁扩散阻挡层基本上是无定形的，并提供优于常规和/或结晶侧壁扩散阻挡层的氢气扩散保护。

5. 发明授权

US06841396B2 VIA0 etch process for FRAM integration 有权
标题翻译：用于FRAM集成的VIA0蚀刻工艺
公开(公告)号：US06841396B2
公开(公告)日：2005-01-11
申请号：US10440697
申请日：2003-05-19
申请人： Francis Gabriel Celii , K. R. Udayakumar , Scott R. Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , K. R. Udayakumar , Scott R. Summerfelt , Theodore S. Moise
IPC分类号： H01L21/00 , H01L21/20 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.
摘要翻译：铁电存储器件包括逻辑可编程电容参考电路。电路适于在感测操作模式期间产生参考电压，其中参考电压包括作为一个以上存储器条件的函数的值。存储器件还包括位线对，其中位线对的第一位线具有耦合的铁电电容器用于感测位线对，并且位线对的第二位线耦合到参考电压。感测电路耦合到位线对，并且被配置为使用与第一位线相关联的电压和第二位线上的参考电压来检测与铁电电容器相关联的数据状态。

6. 发明授权

US06686210B1 Methods for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity 有权
标题翻译：用各向异性铁电极化或介电常数控制薄膜晶体结构的方法
公开(公告)号：US06686210B1
公开(公告)日：2004-02-03
申请号：US09349439
申请日：1999-07-09
申请人： Stephen R. Gilbert , Theodore S. Moise , Scott R. Summerfelt
发明人： Stephen R. Gilbert , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L2100
CPC分类号： H01L28/55 , C23C16/40 , C23C16/409 , C23C16/44 , C23C16/517 , H01L21/31604 , H01L21/31691 , H01L27/0629 , H01L27/0805 , H01L28/60
摘要： A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment resulting in a texture with higher ferroelectric polarization or permittivity which is normally energetically disfavored.
摘要翻译：通过离子轰击来控制具有各向异性铁电极化或介电常数的薄膜的晶体结构的方法，导致通常在能量上不利的铁电极化或介电常数较高的纹理。

7. 发明授权

US06211035B1 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06211035B1
公开(公告)日：2001-04-03
申请号：US09392988
申请日：1999-09-09
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L2120
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

8. 发明授权

US6100200A Sputtering process for the conformal deposition of a metallization or insulating layer 失效
标题翻译：用于金属化或绝缘层的共形沉积的溅射工艺
公开(公告)号：US6100200A
公开(公告)日：2000-08-08
申请号：US218563
申请日：1998-12-21
申请人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
发明人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
IPC分类号： C23C14/04 , C23C14/34 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/311
CPC分类号： H01L28/55 , C23C14/046 , C23C14/34 , H01L21/76877 , H01L21/76895 , H01L21/2855
摘要： The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.
摘要翻译：本发明是涉及在半导体衬底中的沟槽中沉积金属化层的方法。本发明的重点是依次执行加热沉积和蚀刻单元工艺以在通孔或沟槽的内表面上提供良好的金属保形膜。沉积和蚀刻步骤也可以同时进行。

9. 发明授权

US08093070B2 Method for leakage reduction in fabrication of high-density FRAM arrays 有权
标题翻译：高密度FRAM阵列制造中泄漏减少的方法
公开(公告)号：US08093070B2
公开(公告)日：2012-01-10
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译：提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用第二次灰化过程。

10. 发明授权

US06362499B1 Ferroelectric transistors using thin film semiconductor gate electrodes 有权
标题翻译：使用薄膜半导体栅电极的铁电晶体管
公开(公告)号：US06362499B1
公开(公告)日：2002-03-26
申请号：US09645158
申请日：2000-08-24
申请人： Theodore S. Moise , Scott R. Summerfelt
发明人： Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L2976
CPC分类号： G11C29/44 , G11C11/223 , G11C2029/1208 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.
摘要翻译：公开了集成电路中的铁电结构及其制造和使用的方法，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。

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