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81. 发明授权

US07927995B2 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US07927995B2
公开(公告)日：2011-04-19
申请号：US12541502
申请日：2009-08-14
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L21/44
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

82. 发明申请

US20110069425A1 MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US20110069425A1
公开(公告)日：2011-03-24
申请号：US12565802
申请日：2009-09-24
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H01G4/38 , H01L21/02 , H03K17/687
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

83. 发明授权

US07911025B2 Fuse/anti-fuse structure and methods of making and programming same 有权
标题翻译：保险丝/反熔丝结构及制作和编程方法相同
公开(公告)号：US07911025B2
公开(公告)日：2011-03-22
申请号：US12127080
申请日：2008-05-27
申请人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
发明人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译：提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构，其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。还提供了制造和编程保险丝/反熔丝结构的方法。

84. 发明授权

US07902061B2 Interconnect structures with encasing cap and methods of making thereof 有权
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US07902061B2
公开(公告)日：2011-03-08
申请号：US12199407
申请日：2008-08-27
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Theodorus E. Standaert , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Theodorus E. Standaert , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect structure: which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric material; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连结构的方法，其包括在介电材料中提供互连结构，使介电材料凹陷，使得互连结构的一部分在电介质材料的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

85. 发明申请

US20110031623A1 INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION 失效
标题翻译： Cu / ULTRA低k积分的互连结构和方法
公开(公告)号：US20110031623A1
公开(公告)日：2011-02-10
申请号：US12906580
申请日：2010-10-18
申请人： Chih-Chao Yang , Conal E. Murray
发明人： Chih-Chao Yang , Conal E. Murray
IPC分类号： H01L23/52
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76814 , H01L21/76835 , H01L21/76843
摘要： A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided.
摘要翻译：提供了一种半导体结构，其包括下互连级，其包括具有嵌入其中的至少一个导电特征的第一介电材料; 位于所述第一电介质材料上的电介质覆盖层以及所述至少一个导电特征的一些但不是全部的部分; 以及包括具有至少一个导电填充通孔的第二介电材料和布置在其中的上覆导电填充线的上部互连水平，其中所述导电填充的通孔与所述第一互连水平的所述至少一个导电特征的暴露表面接触通过锚定区域。此外，本发明结构的导电填充通孔和导电填充线通过单个连续扩散阻挡层与第二介电材料分离。因此，第二电介质材料在与导电填充线相邻的区域中不包括受损区域。还提供了一种形成这种互连结构的方法。

86. 发明申请

US20110018093A1 PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER 失效
标题翻译： DLC介电层可编程防结构
公开(公告)号：US20110018093A1
公开(公告)日：2011-01-27
申请号：US12509892
申请日：2009-07-27
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.
摘要翻译：在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域第一电介质材料。反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性材料在第二个反熔丝区域。在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。第二电介质材料包括嵌入其中的至少一个导电填充区域。

87. 发明申请

US20100320563A1 ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
标题翻译：半导体集成电路中的电子熔丝
公开(公告)号：US20100320563A1
公开(公告)日：2010-12-23
申请号：US12870921
申请日：2010-08-30
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.
摘要翻译：一个结构。该结构包括：基底; 衬底中的第一电极; 在所述基板和所述电极的顶部上的介电层; 在所述第一介电层上的第二电介质层，所述第二电介质层包括第二电介质材料; 埋入第一介电层中的熔丝元件，其中熔融元件（i）物理分离，（ii）与二者直接物理接触，（iii）被夹在介电层的第一区域和第二区域之间; 以及在所述熔丝元件的顶部上的第二电极，其中所述第一电极和所述第二电极通过所述熔丝元件彼此电耦合。

88. 发明申请

US20100314764A1 HYBRID METALLIC WIRE AND METHODS OF FABRICATING SAME 失效
标题翻译：混合金属线及其制造方法
公开(公告)号：US20100314764A1
公开(公告)日：2010-12-16
申请号：US12482777
申请日：2009-06-11
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.
摘要翻译：一种制造结构的结构和方法。该结构包括：介电层中的沟槽; 导电衬垫，导电芯导体和填充所述衬套和所述芯导体之间的空隙的导电填充材料。

89. 发明授权

US07838873B2 Structure for stochastic integrated circuit personalization 失效
标题翻译：随机集成电路个性化的结构
公开(公告)号：US07838873B2
公开(公告)日：2010-11-23
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L47/00 , H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

90. 发明申请

US20100264543A1 INTERCONNECT STRUCTURE 有权
标题翻译：互连结构
公开(公告)号：US20100264543A1
公开(公告)日：2010-10-21
申请号：US12424843
申请日：2009-04-16
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76847 , H01L21/76805 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.
摘要翻译：公开了用于形成半导体互连结构的互连结构和方法。在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

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