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81. 发明申请

US20060185420A1 Gas sensor 有权
标题翻译：气体传感器
公开(公告)号：US20060185420A1
公开(公告)日：2006-08-24
申请号：US11358621
申请日：2006-02-21
申请人： Shinichi Nakagawa , Yoshihiro Nakano , Masahito Kida , Takio Kojima
发明人： Shinichi Nakagawa , Yoshihiro Nakano , Masahito Kida , Takio Kojima
IPC分类号： G01N7/00
CPC分类号： G01N27/125
摘要： The present invention provides a gas sensor having excellent humidity resistance even if used in a high temperature and high humidity atmosphere. According to the present invention, a gas sensor is comprised of: a silicon substrate; a metal-oxide semiconductor portion comprised mainly of SnO2 and formed on the substrate; and a catalytic portion comprised of Pd and dispersed on a surface of the metal-oxide semiconductor portion, wherein the metal-oxide semiconductor portion and the catalytic portion constitute a gas sensing portion. Furthermore, an insulating portion comprised mainly of SiO2 is formed dispersedly on a surface of the gas sensing portion. Further, the catalytic portion and the insulating portion are formed on the surface of the metal-oxide semiconductor portion so that the surface additive rate, which is expressed by Si/(Pd+Si) representing the ratio in the number of atoms of Si to Pd, of the gas sensing portion having the insulating portion may be 65% or more to 97% or less, and so that the surface additive rate, which is expressed by Si/(Sn+Si) representing the ratio in the number of atoms of Si to Sn, of the gas sensing portion may be 75% or more to 97% or less.
摘要翻译：本发明提供即使在高温高湿环境下使用也具有优异的耐湿性的气体传感器。根据本发明，气体传感器包括：硅衬底; 主要由SnO 2 N 2组成并形成在基板上的金属氧化物半导体部分; 以及由Pd构成并分散在金属氧化物半导体部分的表面上的催化部分，其中金属氧化物半导体部分和催化部分构成气体感测部分。此外，主要由SiO 2 2组成的绝缘部分分散地形成在气体感测部分的表面上。此外，催化剂部分和绝缘部分形成在金属氧化物半导体部分的表面上，使得由Si /（Pd + Si）表示的表示添加剂率表示Si原子数与Si 具有绝缘部分的气体感测部分的Pd可以为65％以上至97％以下，并且表示以表示原子数比的Si /（Sn + Si）表示的表面添加率 Si至Sn的气体检测部分可以为75％以上至97％以下。

82. 发明申请

US20050142322A1 Optical recording media and dipyrrpomethene-metal chelate compounds 审中-公开
标题翻译：光记录介质和二吡咯烷 - 金属螯合物
公开(公告)号：US20050142322A1
公开(公告)日：2005-06-30
申请号：US10507739
申请日：2003-03-27
申请人： Taizo Nishimoto , Shinobu Inoue , Tsutami Misawa , Ryosuke Nara , Yuji Inatomi , Shunsuke Murayama , Tadashi Koike , Yasunori Saito , Shinichi Nakagawa
发明人： Taizo Nishimoto , Shinobu Inoue , Tsutami Misawa , Ryosuke Nara , Yuji Inatomi , Shunsuke Murayama , Tadashi Koike , Yasunori Saito , Shinichi Nakagawa
IPC分类号： C07D209/70 , C07D491/04 , C07D491/048 , C07D495/04 , C09B23/04 , G11B7/246 , G11B7/248 , G11B7/249 , G11B7/2492 , G11B7/253 , G11B7/2534 , G11B7/258 , G11B7/259 , B32B3/02
CPC分类号： C07D495/04 , C07D209/70 , C07D491/04 , C09B23/04 , G11B7/245 , G11B7/246 , G11B7/248 , G11B7/2492 , G11B7/2534 , G11B7/256 , G11B7/259
摘要： An optical recording medium containing in the recording layer a dipyrromethene-metal chelate compound of which the initial principal weight loss temperature is thermogravimetrically from 330° C. through 500° C. inclusive, capable of high speed and high density recording and playback with a laser having a wavelength of 520 to 690 nm.
摘要翻译：在记录层中含有二吡咯亚甲基 - 金属螯合化合物的光学记录介质，其中初始主要重量损失温度由330℃至500℃热重分解，其能够用激光进行高速和高密度的记录和回放具有520至690nm的波长。

83. 发明申请

US20050110071A1 Semiconductor device group and method for fabricating the same, and semiconductor device and method for fabricating the same 有权
标题翻译：半导体器件组及其制造方法，半导体器件及其制造方法
公开(公告)号：US20050110071A1
公开(公告)日：2005-05-26
申请号：US10969240
申请日：2004-10-21
申请人： Taiji Ema , Hideyuki Kojima , Toru Anezaki , Shinichi Nakagawa
发明人： Taiji Ema , Hideyuki Kojima , Toru Anezaki , Shinichi Nakagawa
IPC分类号： H01L27/115 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： The semiconductor group comprises a first semiconductor device including a first design macro and a nonvolatile memory, and a second semiconductor device including a second design macro having identity with the first design macro and including no nonvolatile memory. The first design macro includes a first active region and a first device isolation region formed on a first semiconductor substrate. The second design macro includes a second active region and a second device isolation region formed on a second semiconductor substrate. A curvature radius of an upper end of the first active region in a cross section is larger than a curvature radius of an upper end of the second active region in a cross section. A difference in height between a surface of the first active region and a surface of the first device isolation region is larger than a difference in height between a surface of the second active region and a surface of the device isolation region.
摘要翻译：半导体组包括包括第一设计宏和非易失性存储器的第一半导体器件，以及包括具有与第一设计宏的标识并且不包括非易失性存储器的第二设计宏的第二半导体器件。第一设计宏包括形成在第一半导体衬底上的第一有源区和第一器件隔离区。第二设计宏包括形成在第二半导体衬底上的第二有源区和第二器件隔离区。横截面中第一有源区的上端的曲率半径大于截面中第二有源区的上端的曲率半径。第一有源区的表面与第一器件隔离区的表面之间的高度差大于第二有源区的表面与器件隔离区的表面之间的高度差。

84. 发明授权

US06391721B1 Non-volatile semiconductor memory device having vertical transistors and fabrication method therefor 有权
公开(公告)号：US06391721B1
公开(公告)日：2002-05-21
申请号：US09828222
申请日：2001-04-09
申请人： Shinichi Nakagawa
发明人： Shinichi Nakagawa
IPC分类号： H01L218247
摘要： A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral length of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.

85. 发明授权

US06239465B1 Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor 有权
标题翻译：具有在沟槽中具有浮动和控制栅极的垂直晶体管的非易失性半导体存储器件及其制造方法
公开(公告)号：US06239465B1
公开(公告)日：2001-05-29
申请号：US09391353
申请日：1999-09-08
申请人： Shinichi Nakagawa
发明人： Shinichi Nakagawa
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral width of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.
摘要翻译：开发包括在每个单元中具有沿着沟槽的内壁的垂直沟道的MOS晶体管的非易失性半导体存储单元阵列用于高密度集成和高速操作。本发明的一个方面是形成沟槽，使得具有孔的第一沟槽形成为比半导体表面上的漏极扩散层略深，而具有比第一沟槽小的孔的第二沟槽形成在所述第一沟槽的底部的中心向所述埋入的源极扩散层的深度方向延伸，使得所述漏极区域中的所述第一沟槽的开口部分的外围宽度大于所述源极区域中的所述第二沟槽的开口部分的外围宽度。

86. 发明授权

US5994933A Semiconductor device for controlling a delay time of an output signal of a PLL 失效
标题翻译：用于控制PLL的输出信号的延迟时间的半导体器件
公开(公告)号：US5994933A
公开(公告)日：1999-11-30
申请号：US790016
申请日：1997-01-28
申请人： Tadao Yamanaka , Shinichi Nakagawa
发明人： Tadao Yamanaka , Shinichi Nakagawa
IPC分类号： G11C11/4076 , H03H7/30 , H03K3/03 , H03K3/354 , H03K5/14 , H03L7/08 , H03L7/081 , H03L7/099 , H03B27/00
CPC分类号： H03L7/0996 , H03L7/081
摘要： It is an object to obtain a semiconductor device capable of changing a delay time of an output signal of a PLL circuit with respect to an external clock signal after installed in a system. An external clock signal is inputted to an input terminal (1.) An address value is inputted to an input terminal (3.) A decoder (9) selects one of a plurality of delay times in a voltage-controlled oscillator (8) according to the address value. The phase of a signal outputted to an output terminal (2) is delayed with respect to the external clock signal at the input terminal (1) by the delay time selected. Accordingly, it is possible to change the delay time of the output signal of the PLL circuit with respect to the external clock signal after installation in a system.
摘要翻译：本发明的目的是获得一种半导体器件，其能够在安装在系统中之后改变PLL电路的输出信号相对于外部时钟信号的延迟时间。外部时钟信号被输入到输入端子（1）。地址值被输入到输入端子（3）。解码器（9）根据压控振荡器（8）选择多个延迟时间中的一个，到地址值。输出到输出端子（2）的信号的相位相对于输入端子（1）处的外部时钟信号延迟所选择的延迟时间。因此，可以在系统中改变PLL电路的输出信号相对于外部时钟信号的延迟时间。

87. 发明授权

US5740088A Control signal generating device generating various control signals using storage unit having small storage capacity 失效
标题翻译：控制信号发生装置利用具有小存储容量的存储单元产生各种控制信号
公开(公告)号：US5740088A
公开(公告)日：1998-04-14
申请号：US530497
申请日：1995-09-19
申请人： Shinichi Nakagawa , Kiyofumi Kawamoto , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami
发明人： Shinichi Nakagawa , Kiyofumi Kawamoto , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami
IPC分类号： H03K3/84 , G05B19/07 , G06F7/00 , G06F7/58 , H04L7/00 , G06F1/02
CPC分类号： G05B19/07 , G06F7/00
摘要： A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.
摘要翻译：第一伪随机数产生电路响应于时钟信号顺序地向匹配检测电路提供输出信号。第二伪随机数发生电路产生初始值，然后响应于来自匹配检测电路的输出信号和时钟信号，向存储装置依次提供输出信号。以输出信号作为地址的数据作为来自存储装置的输出信号提供。当匹配检测电路检测输出信号之间的匹配时，匹配检测电路将输出信号提供给第二伪随机数产生电路和与逻辑电路。如上所述，当提供匹配检测电路的输出信号时，来自存储装置的输出信号被提供为相应的输出控制信号。

88. 发明授权

US5717622A Selecting circuit including circuits having different time constants to which each of a plurality of input signals is applied, and adding circuit using the same 失效
标题翻译：包括具有不同时间常数的电路的电路，其中施加了多个输入信号中的每一个，以及使用该电路的加法电路
公开(公告)号：US5717622A
公开(公告)日：1998-02-10
申请号：US463256
申请日：1995-06-05
申请人： Kiyofumi Kawamoto , Shinichi Nakagawa
发明人： Kiyofumi Kawamoto , Shinichi Nakagawa
IPC分类号： G06F7/507 , G06F7/50 , G06F7/501 , G06F7/508 , H03K17/693 , H03K19/0175
CPC分类号： G06F7/501
摘要： A selecting circuit is formed of two tristate gates. The size of each of a plurality of transistors configuring a tristate gate processing a signal having a shorter delay time is set smaller than the size of each of a plurality of transistors configuring a tristate gate processing a signal having a longer delay time, so that the capacitance of the former transistors is decreased. As a result, the load to be driven by each of transistors to which a signal having a longer delay time is applied is decreased, whereby the entire circuit can be increased in operation speed. Accordingly, the selecting circuit selecting between two or more input signals having different delay times can operate at a high speed.
摘要翻译：选择电路由两个三态门形成。构成三态门处理具有较短延迟时间的信号的三态晶体管中的每一个晶体管的尺寸被设置为小于构成三态栅极处理具有较长延迟时间的信号的多个晶体管中的每一个晶体管的尺寸，前一晶体管的电容降低。结果，施加了具有较长延迟时间的信号的晶体管驱动的负载减小，从而可以提高整个电路的工作速度。因此，具有不同延迟时间的两个或多个输入信号之间的选择电路选择可以高速运行。

89. 发明授权

US5479088A Chopper type DC-DC converter 失效
标题翻译：斩波式DC-DC转换器
公开(公告)号：US5479088A
公开(公告)日：1995-12-26
申请号：US279105
申请日：1994-07-22
申请人： Toshiyuki Hayakawa , Hidenobu Ito , Shinichi Nakagawa
发明人： Toshiyuki Hayakawa , Hidenobu Ito , Shinichi Nakagawa
IPC分类号： H02M1/15 , H02M3/155 , H02M3/156 , G05F1/40 , G05F1/44
CPC分类号： H02M3/156 , H02M2001/0009
摘要： The DC-DC converter is disclosed, which has an output terminal connected to an external load, and produces a desired output voltage at the output terminal. An output capacitor in the converter has a first electrode connected to the output terminal and a second electrode. The charge/discharge regulator controls electrical connection between a DC power supply and the output capacitor to permit the capacitor to be charged or discharged. The DC-DC converter includes a first detecting circuit for detecting a change in the output voltage at the output terminal, and a second detecting circuit for detecting a variable load current flowing into the converter from the load via the output terminal. A voltage control circuit is provided in the converter, and controls a potential of the second electrode of the capacitor in such a manner as to nullify a variation in the output voltage, based on a result of detection of the output voltage by the first detecting circuit and on a result of detection of the load current by the second detecting circuit.
摘要翻译：公开了一种DC-DC转换器，其具有连接到外部负载的输出端子，并且在输出端子处产生期望的输出电压。转换器中的输出电容器具有连接到输出端子的第一电极和第二电极。充电/放电调节器控制直流电源和输出电容器之间的电气连接，以允许电容器充电或放电。 DC-DC转换器包括用于检测输出端子处的输出电压变化的第一检测电路和用于检测经由输出端子从负载流入转换器的可变负载电流的第二检测电路。在转换器中设置有电压控制电路，并且基于第一检测电路的输出电压的检测结果，以使得输出电压的变化无效的方式来控制电容器的第二电极的电位并且由第二检测电路检测负载电流的结果。

90. 发明授权

US5400295A Semiconductor integrated circuit device and semiconductor memory device 失效
公开(公告)号：US5400295A
公开(公告)日：1995-03-21
申请号：US976055
申请日：1992-11-13
申请人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
发明人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
IPC分类号： G11C11/417 , G11C7/10 , H01L27/10 , H03K3/356 , G11C11/34
CPC分类号： H03K3/356173 , G11C7/1051 , H03K3/356121
摘要： In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

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