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81. 发明授权

US06249608B1 Template matching image processor utilizing sub image pixel sums and sum of squares thresholding 失效
标题翻译：模板匹配图像处理器利用子图像像素和和平方和阈值
公开(公告)号：US06249608B1
公开(公告)日：2001-06-19
申请号：US08994096
申请日：1997-12-19
申请人： Mitsuji Ikeda , Syoji Yoshida , Keisuke Nakashima , Koyo Katsura , Shigeru Shibukawa , Haruo Yoda , Takashi Hotta
发明人： Mitsuji Ikeda , Syoji Yoshida , Keisuke Nakashima , Koyo Katsura , Shigeru Shibukawa , Haruo Yoda , Takashi Hotta
IPC分类号： G06K962
CPC分类号： G06K9/6203 , G06T7/20
摘要： An image processing apparatus obtains a sum A of image data values of pixels in a template image, a sum B of squares of image data values of pixels in a template image, a sum C of image data values of pixels in a sub-image to be processed, of a search image, a sum D of squares of image data values of pixels in the sub-image of the template image, further obtains a threshold value F in advance by using the obtained values A, B, C and D, the number P of pixels in the template image, and the preset value E. Moreover, the apparatus obtains a square of each difference between an image data value of each pixel in the sub-image and that of a corresponding pixel in the template image, and performs cumulative addition for each obtained squares. If the result of cumulative addition exceeds the above-mentioned threshold value, the apparatus closes processing evaluation of a similarity between the sub-image and the template image. Furthermore, the apparatus recursively obtains a moving-average value of image data values of pixels in a rectangular region to be presently processed, by using a moving-average value for a rectangular region which was previously processed and image data read from a first memory and a second memory, each memory stores image data by one line pixels of the image, which include image data of pertinent pixels in the rectangular regions.
摘要翻译：图像处理装置获得模板图像中的像素的图像数据值的和A，模板图像中的像素的图像数据值的平方和B，子图像中的像素的图像数据值的和C 处理搜索图像，模板图像的子图像中的像素的图像数据值的平方和的和D进一步通过使用获得的值A，B，C和D预先获得阈值F，模板图像中的像素数P和预设值E.此外，该装置获得子图像中的每个像素的图像数据值与模板图像中的对应像素的图像数据值之间的每个差的平方，并对每个获得的正方形执行累积加法。如果累积加法的结果超过上述阈值，则该装置关闭子图像和模板图像之间的相似度的处理评估。此外，该装置通过使用预先处理的矩形区域的移动平均值和从第一存储器读取的图像数据，递归地获得当前处理的矩形区域中的像素的图像数据值的移动平均值，以及第二存储器，每个存储器存储图像的一行像素的图像数据，其包括矩形区域中的相关像素的图像数据。

82. 发明授权

US5935037A Planetary gear transmission 失效
标题翻译：行星齿轮传动
公开(公告)号：US5935037A
公开(公告)日：1999-08-10
申请号：US113193
申请日：1998-07-10
申请人： Takashi Hotta , Takamichi Shimada
发明人： Takashi Hotta , Takamichi Shimada
IPC分类号： F16H3/62 , F16H3/66 , F16D3/66
CPC分类号： F16H3/666 , F16H2200/0047 , F16H2200/201 , F16H2200/2097
摘要： A planetary gear transmission comprises first, second and third planetary gear trains G1, G2 and G3 which are disposed coaxially with one another and respectively in this order from an input member. The first and second ring gears R1 and R2, which are fixedly retainable by a first brake B1, are disengageably connected to the input shaft 1 through a first clutch K1. The first sun gear S1 is also disengageably connected to the input shaft 1 through a third clutch while the first carrier C1 and the second sun gear S2 are connected to the output shaft 7. Furthermore, a connecting shaft 4 is disposed away from and in parallel with the axis of the first, second and third planetary gear trains G1, G2 and G3, and one end of the connecting shaft is connected to the input shaft 1 through a first connecting gear train 2 and 3 while the other end of the connecting shaft is connected to the third sun gear S3 through a second connecting gear train 5 and 6.
摘要翻译：行星齿轮传动装置包括第一，第二和第三行星齿轮系G1，G2和G3，它们分别以输入构件的顺序彼此同轴设置。通过第一制动器B1可固定地保持的第一和第二齿圈R1和R2通过第一离合器K1可分离地连接到输入轴1。第一太阳轮S1也通过第三离合器与输入轴1分离地连接，而第一行星架C1和第二太阳齿轮S2连接到输出轴7.此外，连接轴4远离并且平行与第一，第二和第三行星齿轮系G1，G2和G3的轴线连接，连接轴的一端通过第一连接齿轮系2和3连接到输入轴1，而连接轴的另一端通过第二连接齿轮系5和6连接到第三太阳齿轮S3。

83. 发明授权

US5690579A Planetary gear transmission 失效
标题翻译：行星齿轮传动
公开(公告)号：US5690579A
公开(公告)日：1997-11-25
申请号：US597013
申请日：1996-02-05
申请人： Tomokazu Takeda , Takashi Hotta
发明人： Tomokazu Takeda , Takashi Hotta
IPC分类号： F16H3/66 , F16H3/44
CPC分类号： F16H3/666 , F16H2200/0047 , F16H2200/201
摘要： A planetary gear transmission comprises a first planetary gear train of double pinion type G1 and second and third planetary gear trains of single pinion type G2 and G3 disposed coaxially and in parallel with one another. In this transmission, a first sun gear S1 is coupled to an input member 11 through a first clutch K1, and a first brake B1 is provided for the purpose of selectively holding the first sun gear S1 against rotation. First and second carriers C1 and C2 and a third ring gear R3 are coupled to one another, and these three elements are coupled to the input member 11 through a second clutch K2, and a second brake B2 is provided for the purpose of selectively holding these three elements against rotation. A first ring gear R1 and a second ring gear R2 are coupled with each other, and a third brake B3 is provided for the purpose of selectively holding these two elements against rotation. Second and third sun gears S2 and S3 are coupled with each other, and these two elements are coupled to the input member 11 through a third clutch K3. A third carrier C3 is directly coupled to an output member 12.
摘要翻译：行星齿轮传动装置包括双小齿轮型G1的第一行星齿轮系和同轴并且彼此平行设置的单小齿轮型G2和G3的第二和第三行星齿轮系。在该变速器中，第一太阳轮S1通过第一离合器K1与输入部件11连结，第一制动器B1设置成选择性地保持第一太阳齿轮S1不旋转。第一和第二载体C1和C2以及第三齿圈R3彼此连接，并且这三个元件通过第二离合器K2联接到输入构件11，并且提供第二制动器B2用于选择性地保持这些三个元素反转。第一齿圈R1和第二齿圈R2彼此联接，并且提供第三制动器B3用于选择性地保持这两个元件抵抗旋转。第二和第三太阳齿轮S2和S3彼此联接，并且这两个元件通过第三离合器K3联接到输入构件11。第三载体C3直接耦合到输出构件12。

84. 发明授权

US5539686A Carry propagating device 失效
标题翻译：携带传播装置
公开(公告)号：US5539686A
公开(公告)日：1996-07-23
申请号：US315591
申请日：1994-09-30
申请人： Fumio Murabayashi , Takashi Hotta , Masahiro Iwamura , Akiyoshi Osumi
发明人： Fumio Murabayashi , Takashi Hotta , Masahiro Iwamura , Akiyoshi Osumi
IPC分类号： H03K19/013 , H03K19/0175 , H03K19/018 , G06F7/50
CPC分类号： H03K19/013 , H03K19/017518 , H03K19/01806
摘要： A carry propagating device, provided on a single substrate, is constituted by groups of first and second MOS transistors, a third MOS transistor, a bipolar transistor and first and second impedance elements. An output of the carry propagating device is provided at the collector of the bipolar transistor and is connected to a first power supply terminal through the first impedance element, the emitter is connected to a second power supply terminal through the second impedance element, and the base is connected to a fixed potential source. The first MOS transistors are connected in series between the emitter of the bipolar transistor and the second power supply terminal through the third MOS transistor controlled by a carry signal. As to the second MOS transistors, one is connected in parallel to the second impedance element and each of the remaining ones is connected between a common connection of a respective pair of adjacent ones of the series-connected first MOS transistors and the second power supply terminal. There is thus effected a speed-up of the carry signal and thereby a speeding-up of the signal processing. There is also provided a wiring scheme for preventing noise interference between different wirings. Moreover, a device has been schemed for a plurality of logic circuit blocks and including a data signal path for interconnecting different logic circuit blocks and facilitating the interfacing of a current-driven signal.
摘要翻译：设置在单个基板上的携带传播装置由第一和第二MOS晶体管，第三MOS晶体管，双极晶体管和第一和第二阻抗元件组构成。进位传播装置的输出设置在双极晶体管的集电极处，并通过第一阻抗元件连接到第一电源端子，发射极通过第二阻抗元件连接到第二电源端子，基极连接到固定电位源。第一MOS晶体管通过由进位信号控制的第三MOS晶体管串联连接在双极晶体管的发射极和第二电源端子之间。对于第二MOS晶体管，一个与第二阻抗元件并联连接，其余的每个连接在一对相邻的串联连接的第一MOS晶体管和第二电源端子的公共连接。因此，进行了进位信号的加速，从而加速了信号处理。还提供了用于防止不同布线之间的噪声干扰的布线方案。此外，已经针对多个逻辑电路块设计了一种器件，并且包括用于互连不同逻辑电路块的数据信号路径，并且有助于电流驱动信号的接口。

85. 发明授权

US5117382A Semiconductor integrated circuit for performing an arithmetic operation including bipolar and MOS transistors 失效
标题翻译：用于执行包括双极和MOS晶体管在内的算术运算的半导体集成电路
公开(公告)号：US5117382A
公开(公告)日：1992-05-26
申请号：US618114
申请日：1990-11-26
申请人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
发明人： Hideo Maejima , Takashi Hotta , Ikuro Masuda , Masahiro Iwamura , Kouzaburou Kurita , Masahiro Ueno
IPC分类号： G06F5/01 , G06F7/50 , G06F7/508 , G06F13/40 , G06F15/78
CPC分类号： G06F7/508 , G06F13/4077 , G06F15/7832 , G06F5/015 , G06F2207/3872 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

86. 发明授权

US4939745A Apparatus for generating orthogonal sequences 失效
标题翻译：用于产生正交序列的装置
公开(公告)号：US4939745A
公开(公告)日：1990-07-03
申请号：US399772
申请日：1989-08-28
申请人： Tetsuo Kirimoto , Takashi Hotta , Yoshimasa Ohashi
发明人： Tetsuo Kirimoto , Takashi Hotta , Yoshimasa Ohashi
IPC分类号： H03M7/30 , G01S13/32 , G06F7/544 , H04J13/00 , H04J13/12 , H04L12/00
CPC分类号： H04L12/00 , G01S13/325 , G06F7/544
摘要： An apparatus for generating orthogonal sequences is disclosed which includes an M-sequence generator for providing a signal of M-sequence of which the component takes 0 or 1 and the period is N, and substitution means connected to the output of the M-sequence generator for substituting the component of the M-sequence. The substitution means substitute the component with A.sub.0 e.sup.j.phi..sbsp.0 when the value of the component is 0 and with A.sub.1 e.sup.j.phi..sbsp.1 when it is 1, where each of A.sub.0 and A.sub.1 is a positive real number, and the substitution is performed so that a trigonometric function f.sub.1 (.phi..sub.1 -.phi..sub.0) having a phase of (.phi..sub.1 -.phi..sub.0) is a ratio of two functions f.sub.2 (A.sub.1 /A.sub.0) which is a quadratic function of A.sub.1 /A.sub.0 with a coefficient of a linear function of N and f.sub.3 (A.sub.1 /A.sub.0) which is a linear function of A.sub.1 /A.sub.0 with a coefficient of a linear function of N, whereby the orthogonal sequence is generated from the substitution means.
摘要翻译：公开了一种用于产生正交序列的装置，其包括：M序列发生器，用于提供组件取0或1并且周期为N的M序列的信号，以及连接到M序列发生器的输出的替换装置用于代替M序列的成分。当组件的值为0且A1ej phi 1为1时，替代方法用A0ej phi 0代替组件，其中A0和A1各自为正实数，并执行替换，使得三角函数具有相位（phi1-phi0）的f1（phi1-phi0）是作为A1 / A0的二次函数的函数f2（A1 / A0）与线性函数N的系数的比率 f3（A1 / A0），其为具有线性函数N的系数的A1 / A0的线性函数，由此从替换装置产生正交序列。

87. 发明授权

US4849658A Dynamic logic circuit including bipolar transistors and field-effect transistors 失效
标题翻译：动态逻辑电路包括双极晶体管和场效应晶体管
公开(公告)号：US4849658A
公开(公告)日：1989-07-18
申请号：US81696
申请日：1987-08-04
申请人： Masahiro Iwamura , Takashi Hotta , Hideo Maejima
发明人： Masahiro Iwamura , Takashi Hotta , Hideo Maejima
IPC分类号： H03K19/08 , G06F7/50 , G06F7/501 , G11C7/12 , H03K19/096 , H03K19/177
CPC分类号： G06F7/5016 , G11C7/12 , H03K19/0963 , H03K19/1772 , G06F2207/3872
摘要： A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.
摘要翻译：提供了一种实现高速运行的动态逻辑电路。提供至少一个具有集电极，基极和发射极的双极晶体管，其中集电极 - 发射极电流路径连接在动态逻辑电路的输出端和第一电位之间。预充电装置耦合在第二电位和动态逻辑电路的输出端之间，以根据周期性地改变其状态的至少一个时钟信号对输出进行预充电。此外，提供了至少两个场效应晶体管，其中响应于时钟信号而假定与预充电装置相反的导通或截止状态，而另一个响应于至少一个输入信号而工作。两个场效应晶体管的源极 - 漏极电流路径连接在动态逻辑电路的输出端和双极晶体管的基极之间。

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