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81. 发明授权

US06857100B2 Coding system and decoding system 失效
标题翻译：编码系统和解码系统
公开(公告)号：US06857100B2
公开(公告)日：2005-02-15
申请号：US09983478
申请日：2001-10-24
申请人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
发明人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
IPC分类号： G11B20/18 , G11B27/30 , H04J3/06 , H04L1/00 , H04L7/04 , H04N7/50 , H04N7/56 , H04N7/64 , H04N7/66 , H04N19/89 , H04N21/2383 , H04N21/438 , H04L7/00
CPC分类号： H04N21/435 , G11B20/1813 , G11B27/3027 , H04J3/0602 , H04L1/0041 , H04L1/0045 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/70 , H04N19/89 , H04N21/23424 , H04N21/235 , H04N21/2383 , H04N21/2404 , H04N21/242 , H04N21/4382
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in a code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.
摘要翻译：在其中纠错/检测编码与使用同步码的同步恢复技术组合的编码系统中，解决了由错误检测引起的伪同步和失步的问题。提供了一种用于将输入的多路复用代码串编码到包括信息位和校验位的纠错/检测码的编码部分，以及用于将同步代码插入到多个周期性预定同步代码中的任何一个中的代码串组合部分在代码串中插入位置，用于将信息位布置在代码串中的可选位置处，并且用于将校验位排列在除代码串中的同步代码插入位置之外的位置以组合输出代码串。

82. 发明授权

US06571361B1 Encoder and decoder 有权
标题翻译：编码器和解码器
公开(公告)号：US06571361B1
公开(公告)日：2003-05-27
申请号：US09142871
申请日：1998-09-16
申请人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
发明人： Yoshihiro Kikuchi , Toshiaki Watanabe , Kenshi Dachiku , Takeshi Chujoh , Takeshi Nagai
IPC分类号： H04N752
CPC分类号： H04L1/0042 , G11B20/1813 , G11B27/3027 , H03M13/15 , H03M13/152 , H03M13/23 , H03M13/33 , H03M13/356 , H04J3/0602 , H04L1/0041 , H04L1/0047 , H04L1/0068 , H04L1/007 , H04L1/0075 , H04L1/0079 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/68 , H04N19/70 , H04N19/89
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit; and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
摘要翻译：在将纠错/检测离子编码与使用同步码的同步恢复技术组合的编码系统中，解决了由于错误检测引起的伪同步和失步的问题。提供了一个用于将输入的多路复用代码串201编码到包括信息位和校验位的纠错/检测码的编码部分212; 以及代码串组合部213，用于将代码串201中的多个周期性预定的同步代码插入位置中的任何一个插入同步代码，用于将信息位布置在代码串中的可选位置，并且用于布置校验位在代码串201中的同步代码插入位置以外的位置组合输出代码串205。

83. 发明授权

US06452579B1 Display apparatus 有权
公开(公告)号：US06452579B1
公开(公告)日：2002-09-17
申请号：US09537112
申请日：2000-03-29
申请人： Goh Itoh , Hisao Fujiwara , Hitoshi Kobayashi , Haruhiko Okumura , Noboru Yamaguchi , Toshiaki Watanabe , Yoshihiro Kikuchi , Takashi Ida , Takeshi Chujoh , Yoko Sambonsugi , Takeshi Nagai , Rieko Furukawa
发明人： Goh Itoh , Hisao Fujiwara , Hitoshi Kobayashi , Haruhiko Okumura , Noboru Yamaguchi , Toshiaki Watanabe , Yoshihiro Kikuchi , Takashi Ida , Takeshi Chujoh , Yoko Sambonsugi , Takeshi Nagai , Rieko Furukawa
IPC分类号： G09G336
CPC分类号： G09G3/3659 , G09G3/3648 , G09G2300/0814 , G09G2300/0842 , G09G2310/04 , G09G2320/0257 , G09G2320/103 , G09G2330/021
摘要： A liquid crystal display apparatus comprising a display panel having a plurality of pixels arranged in a matrix, signals lines for inputting a video signal to the plurality of pixels, and switching elements for selecting the pixels individually, a video decoder which decodes input compressed video data to obtain a reconstructed picture signal for each frame, a change region detector for detecting a change region between a previous frame and a current frame by using the reconstructed picture signal, to obtain address data on the change region, a display signal converter for converting the reconstructed picture signal into a display picture signal, a difference signal detector for detecting a difference signal indicating at least a difference between the previous frame and the current frame, a switch driver for selectively driving the switching elements to select the pixels corresponding to the change region in accordance with the address data, and a signal line driver for adding the difference signal and the display picture signal of the previous frame, and inputting an addition result to the signal lines.

84. 发明授权

US06434064B1 Semiconductor memory device having redundancy circuit for saving faulty memory cells 有权
公开(公告)号：US06434064B1
公开(公告)日：2002-08-13
申请号：US09888414
申请日：2001-06-26
申请人： Takeshi Nagai
发明人： Takeshi Nagai
IPC分类号： G11C700
摘要： In a semiconductor memory device comprising a redundancy circuit for saving a faulty memory cell, there are provided a plurality of fuse sets to which a flexible mapping redundancy technique is applied. For at least one of these plurality of fuse sets, there is used a row/column common saving fuse set configured so as to make it available for use in one of row saving and column saving. Even in the case where a number of row faults occur with a memory chip or in the case where a number of column faults occur, the setting of row saving or column saving of a row/column common saving fuse set is adjusted accordingly, whereby saving efficiency is improved, and high saving efficiency in a small area can be achieved.

85. 发明授权

US06372279B1 Sweetener composition 失效
标题翻译：甜味剂组成
公开(公告)号：US06372279B1
公开(公告)日：2002-04-16
申请号：US09707954
申请日：2000-11-08
申请人： Hirotoshi Ishida , Akihiro Kishishita , Takeshi Nagai , Kazutaka Nagashima , Atsuhiko Hirano
发明人： Hirotoshi Ishida , Akihiro Kishishita , Takeshi Nagai , Kazutaka Nagashima , Atsuhiko Hirano
IPC分类号： A23L1236
CPC分类号： A23L27/32
摘要： One embodiment of the present invention provides a sweetener composition, which includes a mixture of N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester, and Acesulfame K, wherein a ratio of the Acesulfame K to a total amount of the N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester and the Acesulfame K is in the range of 10 to 97% by weight, methods of making and of using. Another embodiment of the present invention provides a method for preparing a sweetener composition, which includes drying an A-type crystal of N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester to obtain a C-type crystal of N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester. Another embodiment of the present invention provides a method for producing a sweetener, which includes admixing N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester with Acesulfame K, wherein a ratio of the Acesulfame K to a total amount of the N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester and the Acesulfame K is in the range of 10 to 97% by weight. Another embodiment of the present invention provides a method for improving the dissolution rate of N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester, which includes, prior to dissolving the N-{N-(3,3 -dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester, admixing the N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester with Acesulfame K, wherein a ratio of the Acesulfame K to a total amount of the N-{N-(3,3-dimethylbutyl)-L-&agr;-aspartyl}-L-phenylalanine 1-methyl ester and the Acesulfame K is in the range of 10 to 97% by weight.
摘要翻译：本发明的一个实施方案提供一种甜味剂组合物，其包括N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲酯和乙酰磺胺酸K的混合物，其中a 乙酰磺胺酸钾与N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲酯和乙酰磺胺酸钾的总量的比例在10至97的范围内重量％，制造方法和使用方法。本发明的另一个实施方案提供了一种制备甜味剂组合物的方法，其包括将N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲基得到N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲酯的C型晶体。本发明的另一个实施方案提供了一种生产甜味剂的方法，其包括将N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲酯与乙酰磺胺酸K混合，其中乙酰磺胺酸钾与N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲酯和乙酰磺胺酸钾的总量的比例在10至97的范围内重量％。本发明的另一个实施方案提供了一种改善N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲酯的溶解速率的方法，其包括在溶解 N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲酯，混合N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} L-苯丙氨酸1-甲酯与乙酰磺胺酸K，其中乙酰磺胺酸钾与N- {N-（3,3-二甲基丁基）-L-α-天冬氨酰基} -L-苯丙氨酸1-甲基酯的总量的比例酯和丁磺克烷K的重量百分比在10至97％的范围内。

86. 发明授权

US5300297A Feed additive for ruminants 失效
标题翻译：反刍动物饲料添加剂
公开(公告)号：US5300297A
公开(公告)日：1994-04-05
申请号：US45099
申请日：1993-04-12
申请人： Satoshi Ueda , Takashi Iizuka , Haruo Heima , Makoto Ozawa , Takeshi Nagai , Hiroyuki Sato
发明人： Satoshi Ueda , Takashi Iizuka , Haruo Heima , Makoto Ozawa , Takeshi Nagai , Hiroyuki Sato
IPC分类号： A23K1/00 , A61K9/50 , A23K1/18
CPC分类号： A61K9/501 , A23K40/35 , A61K9/5015 , Y10S426/807
摘要： The present invention relates to a biologically active substance that is stable in the rumen of ruminants and released in the abomasum and its subsequent digestive tract. The biologically active substance has the additional properties of being digested and absorbed with good efficiency.
摘要翻译：本发明涉及在反刍动物的瘤胃中稳定并在皱胃及其随后的消化道中释放的生物活性物质。生物活性物质具有被高效消化吸收的附加特性。

87. 发明授权

US5216404A SiC thin-film thermistor 失效
标题翻译： SIC薄膜热敏电阻
公开(公告)号：US5216404A
公开(公告)日：1993-06-01
申请号：US734691
申请日：1991-07-23
申请人： Takeshi Nagai , Shuji Itou , Kunihiro Tsuruda
发明人： Takeshi Nagai , Shuji Itou , Kunihiro Tsuruda
IPC分类号： H01C1/14
CPC分类号： H01C1/1413 , H01L2924/0002
摘要： A thin-film thermistor element which has an electrically insulating substrate having first and second surfaces opposite to each other and also having a pair of through-holes defined therein so as to extend completely across the thickness thereof, and a pair of electrode films each including a body portion of large surface area and a generally comb-shaped portion continued outwardly from the body portion. The electrode films are formed by the use of a firing process on the first surface of the substrate with the respective comb-shaped portions thereof confronting with each other. First and second electroconductive films are also formed on respective surrounding wall faces defining the corresponding through-holes in the substrate in electrically connected relationship with the body portions of the associated electrode films. A temperature sensitive resistance film is formed by the use of a high frequency sputtering process on the first surface of the substrate so as to overlay the electrode films. A method of making the thermistor element is also disclosed.

88. 发明授权

US5041893A Semiconductor integrated circuit including an intrinsic MOS transistor for generating a reference voltage 失效
标题翻译：包括用于产生参考电压的本征MOS晶体管的半导体集成电路
公开(公告)号：US5041893A
公开(公告)日：1991-08-20
申请号：US560721
申请日：1990-07-31
申请人： Takeshi Nagai , Syuso Fujii
发明人： Takeshi Nagai , Syuso Fujii
IPC分类号： G05F3/24 , H01L27/02
CPC分类号： H01L27/0218 , G05F3/242
摘要： A semiconductor integrated cirucit for generating a reference voltage, including a semiconductor substrate, a first voltage terminal connected to a first voltage source, a resistor connected to the first voltage terminal, a second voltage terminal connected to a second voltage source, an intrinsic MOS and having a source, a drain, a gate and a channel having no ion-implantation for threshold control, a first wiring connected to the resistor and the source, a second wiring connected to the second voltage terminal and the drain, a third wiring connected to the drain and the gate, and an output terminal connected to the first wiring for connecting the resistor to the source. In addition, in one embodiment, there is further provided a power source voltage generating circuit formed in the semiconductor substrate, wherein a reference voltage input terminal of the semiconductor integrated circuit for generating the reference voltage is connected to the reference voltage output terminal, and a predetermined operation is performed in accordance with the potential of the reference voltage input terminal.

89. 发明授权

US5012858A Method of cooling a semiconductor device with a cooling unit, using metal sherbet between the device and the cooling unit 失效
标题翻译：使用冷却单元冷却半导体器件的方法，在器件和冷却单元之间使用金属果汁冻
公开(公告)号：US5012858A
公开(公告)日：1991-05-07
申请号：US334770
申请日：1989-04-10
申请人： Katsuhide Natori , Isao Watanabe , Koji Katsuyama , Isao Kawamura , Haruhiko Yamamoto , Takeshi Nagai
发明人： Katsuhide Natori , Isao Watanabe , Koji Katsuyama , Isao Kawamura , Haruhiko Yamamoto , Takeshi Nagai
IPC分类号： H01L23/373 , H01L23/36 , H01L23/427 , H01L23/473
CPC分类号： H01L23/4275 , H01L2224/16 , H01L2224/73253
摘要： A method of cooling a semiconductor device with a cooling unit, using a metal sherbet, which is metal being in a state of a mixed phase consisting of a liquid phase and a solid phase, as a heat conducting body put between the cooling unit and the semiconductor device for transferring heat generated in the semiconductor device to the cooling unit. The metal sherbet is metal, such as In-Ga binary system, in which solids of In-Ga solid solution are dispersed in an In and Ga liquid at a temperature obtained under normal operations of the semiconductor device and the cooling unit.
摘要翻译：一种冷却装置的冷却装置的冷却装置，其特征在于，在所述冷却装置和所述冷却装置之间，使用由液相和固相构成的混合相的状态下的金属果子露用于将在半导体器件中产生的热传递到冷却单元的半导体器件。金属果汁冻是诸如In-Ga二元体系的金属，其中In-Ga固体的固体在半导体器件和冷却单元的正常操作下获得的温度下分散在In和Ga液体中。

90. 发明授权

US4359372A Method for making a carbide thin film thermistor 失效
标题翻译：制造碳化物薄膜热敏电阻的方法
公开(公告)号：US4359372A
公开(公告)日：1982-11-16
申请号：US196011
申请日：1980-10-10
申请人： Takeshi Nagai , Kazushi Yamamoto , Ikuo Kobayashi
发明人： Takeshi Nagai , Kazushi Yamamoto , Ikuo Kobayashi
IPC分类号： H01C7/04 , H01C17/12 , C23C15/00
CPC分类号： H01C7/041 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/8592 , Y10T29/49085 , Y10T29/49087 , Y10T29/49099 , Y10T29/49101
摘要： A method for making a carbide thin film thermistor which comprises providing an insulating substrate, forming at least one pair of electroconductive electrodes on the substrate in a desired pattern, and forming a carbide resistor film on the insulating substrate and the electroconductive electrodes by sputtering process while leaving part of the electrodes exposed for external connections. A carbide target material is sputtered in an inert gas atmosphere containing a small amount of an impurity gas. The thermistor element is arbitrarily controlled to have a desired level of resistance by choice of the impurity gas, the amount of such gas and the mode of sputtering. Optionally, the element is trimmed to adjust its resistance accurately and is also hermetically sealed within a glass tube to prevent the element from being contaminated with harmful substances.
摘要翻译：一种制造碳化物薄膜热敏电阻的方法，包括提供绝缘基板，以期望的图案在基板上形成至少一对导电电极，并通过溅射工艺在绝缘基板和导电电极上形成碳化物电阻膜，同时将部分电极暴露在外部连接处。碳化物靶材料在含有少量杂质气体的惰性气体气氛中溅射。通过选择杂质气体，这种气体的量和溅射方式，任意地控制热敏电阻元件以具有期望的电阻水平。可选地，修整元件以精确地调整其电阻，并且也气密地密封在玻璃管内以防止元件被有害物质污染。

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