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81. 发明申请

US20090302305A1 SELF-CONSTRAINED ANISOTROPIC GERMANIUM NANOSTRUCTURE FROM ELECTROPLATING 有权
标题翻译：电镀的自约束非均质锗原子纳米结构
公开(公告)号：US20090302305A1
公开(公告)日：2009-12-10
申请号：US12541559
申请日：2009-08-14
申请人： Guy Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
发明人： Guy Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
IPC分类号： H01L29/12
CPC分类号： C25D3/54 , B82Y10/00 , C25D5/022 , C25D7/123 , H01L21/0237 , H01L21/02532 , H01L21/02603 , H01L21/02628 , H01L21/02639 , Y10S977/762
摘要： A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.
摘要翻译：提供包括锗的纳米结构，其包括直径小于1微米的导线和宽度小于1微米的与基底接触并从基底向外延伸的纳米结构以及制备方法。

82. 发明申请

US20090231915A1 Reading array cell with matched reference cell 有权
标题翻译：读取具有匹配参考单元格的阵列单元
公开(公告)号：US20090231915A1
公开(公告)日：2009-09-17
申请号：US12292654
申请日：2008-11-24
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C16/04 , G11C7/02 , G11C16/06 , H01L21/336
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

83. 发明申请

US20080064149A1 STRAINED-CHANNEL FIN FIELD EFFECT TRANSISTOR (FET) WITH A UNIFORM CHANNEL THICKNESS AND SEPARATE GATES 有权
公开(公告)号：US20080064149A1
公开(公告)日：2008-03-13
申请号：US11927893
申请日：2007-10-30
申请人： Guy Cohen
发明人： Guy Cohen
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/7842 , H01L29/78687 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

84. 发明申请

US20080050887A1 METHOD FOR FABRICATING SiGe-ON-INSULATOR (SGOI) AND Ge-ON-INSULATOR (GOI) SUBSTRATES 有权
标题翻译：用于制造SiGe-ON绝缘体（SGOI）和Ge-ON-Insulator（GOI）衬底的方法
公开(公告)号：US20080050887A1
公开(公告)日：2008-02-28
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

85. 发明申请

US20070133276A1 Operating array cells with matched reference cells 有权
标题翻译：具有匹配参考单元的操作阵列单元
公开(公告)号：US20070133276A1
公开(公告)日：2007-06-14
申请号：US11580995
申请日：2006-10-16
申请人： Eli Lusky , Boaz Eitan , Guy Cohen
发明人： Eli Lusky , Boaz Eitan , Guy Cohen
IPC分类号： G11C16/04
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括待读取的位和至少一个其他不被读取的位的存储单元，以及读取所述位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

86. 发明申请

US20060273389A1 Vertical FET with nanowire channels and a silicided bottom contact 有权
标题翻译：具有纳米线通道的垂直FET和硅底部接触
公开(公告)号：US20060273389A1
公开(公告)日：2006-12-07
申请号：US11135227
申请日：2005-05-23
申请人： Guy Cohen , Paul Solomon
发明人： Guy Cohen , Paul Solomon
IPC分类号： H01L29/76
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/0237 , H01L21/02381 , H01L21/02433 , H01L21/02521 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02645 , H01L21/02653 , H01L29/045 , H01L29/0676 , H01L29/66666 , H01L29/7827 , H01L29/7828 , Y10S977/762 , Y10S977/938
摘要： A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.
摘要翻译：公开了一种具有形成FET沟道的纳米线的垂直FET结构。纳米线形成在导电硅化物层上。纳米线由周围的门浇口。顶部和底部绝缘体插塞用作栅极间隔，并减少栅极 - 源极和栅极 - 漏极电容。

87. 发明授权

US07136304B2 Method, system and circuit for programming a non-volatile memory array 有权
标题翻译：用于编程非易失性存储器阵列的方法，系统和电路
公开(公告)号：US07136304B2
公开(公告)日：2006-11-14
申请号：US10695449
申请日：2003-10-29
申请人： Guy Cohen , Boaz Eitan
发明人： Guy Cohen , Boaz Eitan
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5671 , G11C16/10 , G11C16/3468
摘要： The present invention is a multi-phase method, circuit and system for programming non-volatile memory (“NVM”) cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds to first intermediate voltage, and to cause a charge pump circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.
摘要翻译：本发明是用于在NVM阵列中编程非易失性存储器（“NVM”）单元的多相方法，电路和系统。本发明可以包括控制器，用于确定在第一编程阶段期间，第一组单元的一个或多个NVM单元何时达到或超过第一中间电压，并且使电荷泵电路施加到第一组第二阶段中的一个或多个单元编程脉冲，以在具有较少存储电荷的单元中产生相对较大的阈值电压变化，具有相对较多存储电荷的单元。

88. 发明申请

US20060126382A1 Method for reading non-volatile memory cells 有权
标题翻译：读取非易失性存储单元的方法
公开(公告)号：US20060126382A1
公开(公告)日：2006-06-15
申请号：US11007332
申请日：2004-12-09
申请人： Eduardo Maayan , Guy Cohen , Boaz Eitan
发明人： Eduardo Maayan , Guy Cohen , Boaz Eitan
IPC分类号： G11C16/06
CPC分类号： G11C29/28 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/50 , G11C29/50004
摘要： A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell, selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells associated with the at least one history cell using the memory read reference level.
摘要翻译：一种方法包括根据不同组存储器单元的阈值电压分布的变化来改变用于读取一组存储器单元的读取参考电平。改变步骤包括确定用于正确读取至少一个历史单元的历史读取参考电平，根据第一读取参考电平选择存储器读取参考电平，以及读取与至少一个历史单元相关联的非易失性存储器阵列单元使用内存读取参考级别。

89. 发明申请

US20050205932A1 Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates 失效
标题翻译：应变通道Fin场效应晶体管（FET）具有均匀的沟道厚度和分离的栅极
公开(公告)号：US20050205932A1
公开(公告)日：2005-09-22
申请号：US11117424
申请日：2005-04-29
申请人： Guy Cohen
发明人： Guy Cohen
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/10 , H01L29/786
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/7842 , H01L29/78687 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.
摘要翻译：半导体器件（及其制造方法）包括邻近源极和漏极形成的应变硅沟道，在沟道的第一侧上形成的第一栅极，在沟道的第二侧上形成的第二栅极，形成在第一栅极和应变硅沟道之间的第一栅极电介质，以及形成在第二栅极和应变硅沟道之间的第二栅极电介质。应变硅通道是非平面的。

90. 发明申请

US20050124146A1 Method of fabricating strained Si SOI wafers 失效
公开(公告)号：US20050124146A1
公开(公告)日：2005-06-09
申请号：US10728519
申请日：2003-12-05
申请人： Steven Bedell , Guy Cohen , Huajie Chen
发明人： Steven Bedell , Guy Cohen , Huajie Chen
IPC分类号： H01L21/20 , H01L21/324 , H01L21/762 , H01L21/425
CPC分类号： H01L21/324
摘要： A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate in which the strained semiconductor is a thin semiconductor layer having a thickness of less than 50 nm that is located directly atop an insulator layer of a preformed silicon-on-insulator substrate is provided. Wafer bonding is not employed in forming the SSOI substrate of the present invention.

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