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81. 发明授权

US09425288B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09425288B2
公开(公告)日：2016-08-23
申请号：US14412237
申请日：2012-07-18
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/268 , H01L21/76283 , H01L29/665 , H01L29/785
摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
摘要翻译：提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域半导体鳍片延伸。随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源/漏区接触。本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

82. 发明授权

US08716095B2 Manufacturing method of gate stack and semiconductor device 有权
标题翻译：栅极堆叠和半导体器件的制造方法
公开(公告)号：US08716095B2
公开(公告)日：2014-05-06
申请号：US12997625
申请日：2010-09-19
申请人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
发明人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/513 , H01L21/28176 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78
摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.
摘要翻译：具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边门堆栈结构。通过该方法制造的半导体器件。

83. 发明授权

US08642433B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08642433B2
公开(公告)日：2014-02-04
申请号：US13509551
申请日：2011-12-05
申请人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/336 , H01L21/477
CPC分类号： H01L29/6653 , H01L29/78
摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.
摘要翻译：公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

84. 发明申请

US20130045588A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130045588A1
公开(公告)日：2013-02-21
申请号：US13509551
申请日：2011-12-05
申请人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/20
CPC分类号： H01L29/6653 , H01L29/78
摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.
摘要翻译：公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

85. 发明申请

US20120286373A1 GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：门结构及其制造方法
公开(公告)号：US20120286373A1
公开(公告)日：2012-11-15
申请号：US13376501
申请日：2011-04-26
申请人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
发明人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/6653
摘要： Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value.
摘要翻译：公开了用于制造其门的结构和方法。在一个示例中，栅极结构包括形成在半导体衬底上的栅极堆叠，栅堆叠包括从底部到顶部的高K电介质层和金属栅电极; 位于所述栅极叠层的侧壁上的第一介电层，所述第一介电层用作第一侧壁间隔物; 以及在所述第一电介质层上的牺牲金属层，所述牺牲金属层用作第二侧壁间隔物。栅极结构中的牺牲金属层在退火步骤中减小界面氧化物层的厚度。栅极结构可以应用于具有小尺寸的半导体器件，因为栅极介电层具有低的EOT值。

86. 发明授权

US08278721B2 Contact hole, semiconductor device and method for forming the same 有权
标题翻译：接触孔，半导体器件及其形成方法
公开(公告)号：US08278721B2
公开(公告)日：2012-10-02
申请号：US13119513
申请日：2011-02-24
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/02
CPC分类号： H01L21/76897 , H01L21/76831 , H01L29/41783 , H01L29/6653 , H01L29/6656
摘要： The invention provides a method for forming a contact plug, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, the sacrificial sidewall spacer material being different from that of the gate, the sidewall spacer and the interlayer dielectric layer; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.
摘要翻译：本发明提供一种用于形成接触塞的方法，包括：在基底上形成栅极，侧壁间隔物，牺牲侧壁间隔物，源极区和漏极区，其中侧壁间隔物围绕栅极形成，牺牲侧壁间隔物形成在侧壁间隔物上，并且源极区和漏极区形成在衬底内和栅极的相应侧上; 形成层间电介质层，其中所述栅极，所述侧壁间隔物和所述牺牲侧壁间隔物被暴露; 去除所述牺牲侧壁间隔物以形成接触空间，所述牺牲侧壁间隔物材料与所述牺牲侧壁间隔物材料不同于所述牺牲侧壁间隔物，形成导电层以填充接触空间; 并切断导电层，形成分别连接到源区和漏区的至少两个导体。

87. 发明申请

US20110233722A1 CAPACITOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：电容器结构及其制造方法
公开(公告)号：US20110233722A1
公开(公告)日：2011-09-29
申请号：US12993048
申请日：2010-09-21
申请人： Qingqing Liang , Huicai Zhong
发明人： Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/90 , H01G4/232 , H01G4/30 , H01G4/33 , H01L28/86
摘要： The presented application discloses a capacitor structure and a method for manufacturing the same. The capacitor structure comprises a plurality of sub-capacitors formed on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween; and a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel, wherein the plurality of sub-capacitors includes a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitor, with the overlapping plate being a second electrode layer, the capacitor structure is characterized in that the first electrode layer and the second electrode layers are made of different conductive materials. The capacitor structure has a small footprint on the chip and a large capacitance value, and can be used as an integrated capacitor in an analogous circuit, an RF circuit, an embedded memory, and the like.
摘要翻译：本申请公开了一种电容器结构及其制造方法。电容器结构包括形成在基板上的多个子电容器，每个子电容器包括顶部电容器板，底部电容器板和夹在其间的电介质层; 以及并联连接多个副电容器的第一电容电极和第二电容电极，其中，所述多个副电容器包括多个第一子电容器和以交替方式堆叠的多个第二子电容器，的第一子电容器具有与下面的第二子电容器的顶部电容器板重叠的底部电容器板，其中重叠板是第一电极层，并且每个第二子电容器具有与电容器结构的特征在于，第一电极层和第二电极层由不同的导电材料制成。电容器结构在芯片上具有小的占地面积和大的电容值，并且可以用作模拟电路，RF电路，嵌入式存储器等中的集成电容器。

88. 发明授权

US09711612B2 Semiconductor device structure and method for fabricating the same 有权
公开(公告)号：US09711612B2
公开(公告)日：2017-07-18
申请号：US13003969
申请日：2010-09-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/49 , H01L21/768 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L29/66545 , H01L29/78
摘要： A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.

89. 发明授权

US09293377B2 Semiconductor device structure and method for manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US09293377B2
公开(公告)日：2016-03-22
申请号：US13266607
申请日：2011-08-10
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823871
摘要： There are provided a semiconductor device structure and a method for manufacturing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source/drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gates of respective unit devices, and isolated portions of the conductive spacer form contacts of respective unit devices. Embodiments of the present disclosure are applicable to manufacture of contacts in integrated circuits.
摘要翻译：提供半导体器件结构及其制造方法。该方法包括：在半导体衬底上形成至少一条连续的栅极线; 形成围绕所述栅极线的栅极间隔; 在栅极线的两侧形成半导体衬底中的源/漏区; 形成围绕所述栅极间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中所述栅极线的隔离部分形成各个单元器件的栅极，并且所述导电间隔物的隔离部分形成各个单元器件的触点。本公开的实施例可应用于集成电路中的触点的制造。

90. 发明授权

US08686534B2 Trench isolation structure and method for forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US08686534B2
公开(公告)日：2014-04-01
申请号：US13145301
申请日：2011-04-22
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232 , H01L29/02
摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
摘要翻译：提供了沟槽隔离结构及其形成方法。沟槽隔离结构包括：半导体衬底和形成在半导体衬底中并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

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