专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08637935B2 Semiconductor device including embedded isolation regions and method for forming the same 有权
标题翻译：包括嵌入式隔离区的半导体器件及其形成方法
公开(公告)号：US08637935B2
公开(公告)日：2014-01-28
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

2. 发明申请

US20120132923A1 SUBSTRATE FOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME 有权
标题翻译：用于集成电路的基板及其形成方法
公开(公告)号：US20120132923A1
公开(公告)日：2012-05-31
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/161 , H01L29/20 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

3. 发明申请

US20120126245A1 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：浅层分离结构及其形成方法
公开(公告)号：US20120126245A1
公开(公告)日：2012-05-24
申请号：US13132068
申请日：2011-01-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L21/762 , H01L29/12 , H01L29/06 , H01L29/16 , B82Y40/00 , B82Y99/00
CPC分类号： H01L21/76232
摘要： The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其形成方法。 STI结构包括半导体衬底; 第一沟槽，其嵌入在所述半导体衬底中并填充有第一介电层; 以及形成在所述半导体衬底的顶表面上并与所述第一沟槽互连的第二沟槽，其中所述第二沟槽填充有第二介电层，所述第二介电层的顶表面与所述半导体衬底的顶表面冲洗，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减小了图形的尺寸并提高了半导体器件的性能。

4. 发明申请

US20120126244A1 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：浅层分离结构及其形成方法
公开(公告)号：US20120126244A1
公开(公告)日：2012-05-24
申请号：US13119004
申请日：2011-01-27
申请人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
IPC分类号： H01L29/12 , H01L29/16 , H01L21/761 , H01L27/04 , H01L21/762
CPC分类号： H01L29/7846 , H01L21/76224
摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减少了对于半导体器件性能的影响。

5. 发明申请

US20120025317A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20120025317A1
公开(公告)日：2012-02-02
申请号：US13003969
申请日：2010-09-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L29/66545 , H01L29/78
摘要： A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.
摘要翻译：一种半导体器件结构及其制造方法。一种制造半导体器件结构的方法包括在半导体衬底上形成栅极线; 形成围绕所述栅极线的栅极侧壁间隔物; 在半导体衬底中和各个栅极线的任一侧上形成相应的源/漏区; 形成围绕所述栅极侧壁间隔物的导电侧壁间隔物并且在切割栅极线是电隔离栅极的预定位置处切断栅极线，栅极侧壁间隔物和导电侧壁间隔物，并且切割的导电侧壁间隔物是电隔离的下部触点。该方法适用于集成电路中触点的制造。

6. 发明授权

US09048286B2 Substrate for integrated circuit and method for forming the same 有权
标题翻译：集成电路基板及其形成方法
公开(公告)号：US09048286B2
公开(公告)日：2015-06-02
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

7. 发明授权

US08525188B2 Shallow trench isolation structure and method for forming the same 有权
标题翻译：浅沟隔离结构及其形成方法
公开(公告)号：US08525188B2
公开(公告)日：2013-09-03
申请号：US13132068
申请日：2011-01-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L31/0312 , H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/76232
摘要： The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其形成方法。 STI结构包括半导体衬底; 第一沟槽，其嵌入在所述半导体衬底中并填充有第一介电层; 以及形成在所述半导体衬底的顶表面上并与所述第一沟槽互连的第二沟槽，其中所述第二沟槽填充有第二介电层，所述第二介电层的顶表面与所述半导体衬底的顶表面冲洗，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减小了图形的尺寸并提高了半导体器件的性能。

8. 发明授权

US08269307B2 Shallow trench isolation structure and method for forming the same 有权
标题翻译：浅沟隔离结构及其形成方法
公开(公告)号：US08269307B2
公开(公告)日：2012-09-18
申请号：US13119004
申请日：2011-01-27
申请人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
IPC分类号： H01L29/15
CPC分类号： H01L29/7846 , H01L21/76224
摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减少了对于半导体器件性能的影响。

9. 发明申请

US20120187496A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120187496A1
公开(公告)日：2012-07-26
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

10. 发明授权

US09711612B2 Semiconductor device structure and method for fabricating the same 有权
公开(公告)号：US09711612B2
公开(公告)日：2017-07-18
申请号：US13003969
申请日：2010-09-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/49 , H01L21/768 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L29/66545 , H01L29/78
摘要： A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式