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81. 发明授权

US6103601A Method and apparatus for improving film stability of halogen-doped silicon oxide films 有权
标题翻译：用于提高卤素掺杂氧化硅膜的膜稳定性的方法和装置
公开(公告)号：US6103601A
公开(公告)日：2000-08-15
申请号：US330247
申请日：1999-06-10
申请人： Peter W. Lee , Stuardo Robles , Anand Gupta , Virendra V. S. Rana , Amrita Verma
发明人： Peter W. Lee , Stuardo Robles , Anand Gupta , Virendra V. S. Rana , Amrita Verma
IPC分类号： H01L21/768 , C23C16/40 , C23C16/56 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L23/522 , H01L21/425 , H01L21/469
CPC分类号： H01L21/02131 , C23C16/401 , C23C16/56 , H01L21/02274 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31629
摘要： A fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment step includes forming a thin, undoped silicate glass layer on top of the FSG layer, and in another embodiment, the stability of the FSG film is increased by a post-treatment plasma step.
摘要翻译：描述了具有低介电常数的氟掺杂硅酸盐玻璃（FSG）层和形成这种绝缘层的方法。 FSG层通过后处理步骤进行处理，以使该层对氟原子的吸湿和除气有抵抗作用。在一个实施方案中，后处理步骤包括在FSG层的顶部上形成薄的未掺杂的硅酸盐玻璃层，在另一个实施方案中，通过后处理等离子体步骤来增加FSG膜的稳定性。

82. 发明授权

US6023188A Positive/negative high voltage charge pump system 有权
标题翻译：正/负高压电荷泵系统
公开(公告)号：US6023188A
公开(公告)日：2000-02-08
申请号：US232115
申请日：1999-01-15
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G05F3/20 , G11C5/14 , G11C11/56 , G11C16/14 , G11C16/16 , G11C16/30 , H02M3/07 , G05F3/02
CPC分类号： G05F3/20 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/14 , G11C16/16 , G11C16/30 , G11C5/145 , H02M3/073
摘要： A two-phase high voltage generator circuit is electronically reconfigurable to output positive (V.sub.Pp) or negative (V.sub.Pn) high voltage, depending upon whether positive or negative mode operation is selected. The circuit includes a plurality of series-connected charge multiplier stages that each comprises a MOS transistor and a charging capacitor. Collectively the stages define an anode node and a cathode node. One of two non-overlapping phase signals is coupled to the free end of each charging capacitor such that adjacent charging capacitors are driven by different phases. First and second two-way multiplexers (MUX1, MUX2) control voltages presented to the anode and cathode nodes, to determine whether circuit operation is positive or negative mode. The MOS devices may be PMOS or NMOS, and preferably Vt-cancellation is provided for each charging stage. A precharge/discharge circuit preferably is coupled to each voltage node including the load capacitor. Further, substrate-well protection is provided such that the MOS devices are less prone to exhibit voltage breakdown or substrate to source/drain current flow.
摘要翻译：根据是选择正还是负模式操作，两相高压发生器电路是电子可重新配置的，以输出正（VPp）或负（VPn）高电压。电路包括多个串联连接的电荷倍增器级，每个级包括MOS晶体管和充电电容器。这些阶段总共定义了阳极节点和阴极节点。两个非重叠相位信号中的一个耦合到每个充电电容器的自由端，使得相邻的充电电容器由不同的相位驱动。第一和第二双向多路复用器（MUX1，MUX2）提供给阳极和阴极节点的控制电压，以确定电路操作是正还是负模式。 MOS器件可以是PMOS或NMOS，并且优选地为每个充电阶段提供Vt消除。预充电/放电电路优选地耦合到包括负载电容器的每个电压节点。此外，提供衬底井保护，使得MOS器件不太容易出现电压击穿或衬底到源极/漏极电流。

83. 发明授权

US5953255A Low voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced endurance 失效
标题翻译：低电压，低电流热孔注入擦除和热电子可编程闪存，具有更强的耐用性
公开(公告)号：US5953255A
公开(公告)日：1999-09-14
申请号：US998418
申请日：1997-12-24
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： G11C11/56 , G11C16/10 , G11C16/16 , G11C11/40
CPC分类号： G11C16/16 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C2211/565
摘要： An array of MOS memory cells having functionally symmetrical drain and source regions may be programmed and/or erased using low voltage, e.g., less than about 7V. In a NAND-type array, UV-erasure increases threshold voltage Vt to erase memory cell contents, and low voltage-low current hot-hole injection ("HHI") decreases Vt to program the memory cells. For NOR-type arrays, HHI decreases Vt to erase memory cell contents and channel-hot-electron ("CHE") injection increases Vt to program cell contents. Erase and program potentials are low (
摘要翻译：具有功能对称的漏极和源极区域的MOS存储器单元的阵列可以使用低电压（例如小于约7V）被编程和/或擦除。在NAND型阵列中，UV擦除增加阈值电压Vt以擦除存储单元内容，而低电压 - 低电流热空穴注入（“HHI”）减小Vt以对存储单元进行编程。对于NOR型阵列，HHI减小Vt以擦除存储单元内容，并且通道热电子（“CHE”）注入增加Vt以编程单元内容。擦除和编程电位低（<7V），使得阵列可以在具有低压电路的公共IC上轻松制造。由于HHI强烈收敛Vt，存储单元可能存储两个以上的数据值，这增加了单元存储密度。电池对称性允许在电池耐久性变得太麻烦之前交换源的漏极，这种交换可以显着增加阵列的耐久寿命。阵列可用作闪速存储器，如EPROM替换，或作为一次可编程存储器。

84. 发明授权

US5914896A Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices 失效
标题翻译：使用薄氧化物和厚氧化物半导体器件的高速擦除结构的闪存
公开(公告)号：US5914896A
公开(公告)日：1999-06-22
申请号：US915344
申请日：1997-08-22
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/56 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3418 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3431 , H01L27/115 , G11C16/30 , G11C2211/5621 , G11C2211/5642 , G11C2211/5645 , G11C8/00 , G11C8/14
摘要： A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline. Another embodiment of the invention increases the selected sourceline voltage to achieve a high voltage differential between the gate and source of flash transistors selected to be erased. In another second embodiment, the wordline decoder is constructed from thin oxide and thick oxide semiconductor devices. Thick oxide devices are used in the wordline driver, which allows an increased voltage differential to be applied to the wordlines without damaging the wordline driver. Advantages of the invention include a fast erasing procedure due to the increased voltage differential applied between the gate and source of flash transistors selected to be erased.
摘要翻译：具有高速擦除结构的闪速存储器包括具有多个字线的组闪存晶体管，多个位线和源极线。字线解码器耦合到字线并且被配置为选择性地向字线施加电压以对闪存晶体管执行过程，其中过程包括读取过程，擦除过程和程序过程。在擦除过程期间，字线解码器被配置为将第一电压范围中的第一越来越大的负电压施加到至少一个选定字线，直到满足第一阈值电压，然后在第二电压范围内施加第二越来越大的负电压，并且将第三电压范围中的第三负电压同时施加到至少一个取消选择的字线。本发明的另一实施例增加了所选择的源极线电压，以实现选择被擦除的闪光晶体管的栅极和源极之间的高电压差。在另一第二实施例中，字线解码器由薄氧化物和厚氧化物半导体器件构成。在字线驱动器中使用厚的氧化物装置，这允许将增加的电压差施加到字线而不损害字线驱动器。本发明的优点包括快速擦除程序，这是由于在被选择被擦除的闪光晶体管的栅极和源极之间施加的电压差增大。

85. 发明授权

US5777923A Flash memory read/write controller 失效
标题翻译：闪存读/写控制器
公开(公告)号：US5777923A
公开(公告)日：1998-07-07
申请号：US664639
申请日：1996-06-17
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , G11C11/34
CPC分类号： G11C16/3418 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3413 , G11C16/3431 , G11C8/08 , H01L27/115 , G11C16/08 , G11C16/24 , G11C2211/5644 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory includes a flash transistor array, a wordline decoder, a bitline decoder, a sourceline decoder and a read/write controller. The read/write controller has a voltage terminal to receive an input voltage and a data terminal to receive a new data signal. A sense amplifier is coupled to the bitline decoder and configured to sense a signal on a selected bitline and to generate an internal old data signal. A data comparator is coupled to the data terminal and the sense amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to read a selected cell in the flash transistor array, a program set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.
摘要翻译：闪速存储器包括闪存晶体管阵列，字线解码器，位线解码器，源线解码器和读/写控制器。读/写控制器具有用于接收输入电压的电压端子和用于接收新数据信号的数据端子。感测放大器耦合到位线解码器并且被配置为感测所选位线上的信号并产生内部旧数据信号。数据比较器耦合到数据终端和读出放大器，并被配置为将新数据信号与旧数据信号进行比较并产生比较器信号。电压发生器被配置为选择性地施加读取的一组电压以读取闪存晶体管阵列中的所选择的单元，编程所选择的单元的电压的编程组和擦除所选择的单元的擦除组。在多状态实施例中，读/写控制器还包括配置成产生多个步数的步数计数器。电压发生器耦合到台阶计数器并且被配置为基于步数产生字线高电压（WLHV）信号。 WLHV信号由字线解码器传送到选定的多状态单元，以读取所选择的多状态单元的内容。每个步骤都比较旧数据和新数据，以确定要更改的存储单元。本发明的优点包括增加编程和擦除的灵活性并改善记忆寿命。

86. 发明授权

US5774396A Flash memory with row redundancy 失效
标题翻译：具有行冗余的闪存
公开(公告)号：US5774396A
公开(公告)日：1998-06-30
申请号：US762707
申请日：1996-12-09
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： The invention provides a flash memory with row redundancy. The memory includes an input terminal to receive an address and a command signal. A plurality of flash memory arrays are arranged as blocks, where each block includes a plurality of transistors organized in rows and columns and having respective wordlines, bitlines and a sourceline. A wordline decoder is coupled to the input terminal and a portion of the plurality of blocks and configured to decode a portion of the address and to receive a control signal to selectively apply a predetermined voltage to a wordline. A bitline decoder is coupled to the input terminal and to the plurality of blocks and configured to decode a portion of the address and to selectively pass a predetermined bitline to an output terminal. A match circuit is coupled to the input terminal and to a portion of the plurality of blocks and configured to decode a portion of the address and to receive the control signal to selectively apply a predetermined voltage to a wordline. A control circuit is coupled to the wordline decoder and the match circuit and configured to selectively activate one of the wordline decoder and the match circuit by the control signal. Advantages of the invention include improved row redundancy for wordline replacement and block replacement.
摘要翻译：本发明提供具有行冗余性的闪速存储器。存储器包括用于接收地址和命令信号的输入端。多个闪速存储器阵列被布置为块，其中每个块包括以行和列组织的多个晶体管，并且具有相应的字线，位线和源极线。字线解码器耦合到输入端和多个块的一部分，并且被配置为对地址的一部分进行解码，并且接收控制信号以选择性地将预定电压施加到字线。位线解码器耦合到输入端和多个块并且被配置为对地址的一部分进行解码，并选择性地将预定位线传递到输出端。匹配电路耦合到输入端和多个块的一部分，并且被配置为对地址的一部分进行解码并接收控制信号以选择性地将预定电压施加到字线。控制电路耦合到字线解码器和匹配电路，并且被配置为通过控制信号选择性地激活字线解码器和匹配电路中的一个。本发明的优点包括改进用于字线替换和块替换的行冗余。

87. 发明授权

US5748545A Memory device with on-chip manufacturing and memory cell defect detection capability 失效
标题翻译：具有片上制造和存储单元缺陷检测能力的存储器件
公开(公告)号：US5748545A
公开(公告)日：1998-05-05
申请号：US834775
申请日：1997-04-03
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C29/02 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/02 , G06F2201/81
摘要： A memory device with an on-chip manufacturing and memory cell defect detection capability includes a memory array with a plurality of memory cells that are organized in rows and columns, a plurality of word lines that interconnect respectively the rows of memory cells, and a plurality of bit lines that interconnect respectively the columns of memory cells. Global word line short and global word line open testing circuits are provided to detect the presence of a word line short or word line open condition. Local word line short and local word line open testing circuits are provided to identify the defective word line. Global bit line short and global bit line open testing circuits are provided to detect the presence of a bit line short or bit line open condition. A local bit line short/open testing circuit is used to identify the defective bit line. Short circuiting between word lines and bit lines, and the maximum and minimum threshold voltages of the memory cells can also be detected in the disclosed memory device.
摘要翻译：具有片上制造和存储单元缺陷检测能力的存储器件包括：存储器阵列，其具有以行和列组织的多个存储器单元;分别互连存储器单元的行的多条字线;以及多个的位线，分别互连存储器单元的列。提供全局字线短和全局字线打开测试电路，以检测字线短或字线打开状态的存在。提供本地字线短路和本地字线打开测试电路以识别有缺陷的字线。提供全局位线短路和全局位线开路测试电路，以检测位线短路或位线开路状况的存在。本地位线短路/开路测试电路用于识别有缺陷的位线。在所公开的存储器件中也可以检测字线和位线之间的短路以及存储单元的最大和最小阈值电压。

88. 发明授权

US5748538A OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array 失效
标题翻译：用于具有基于位的写入能力的闪存的OR平面存储单元阵列，以及用于编程和擦除存储单元阵列的方法
公开(公告)号：US5748538A
公开(公告)日：1998-05-05
申请号：US746665
申请日：1996-11-14
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C8/12 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/3459 , G11C8/08 , G11C8/10 , G11C8/12 , H01L27/115 , G11C16/24 , G11C2211/5644 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）的存储单元阵列包括以行和列排列的多个晶体管单元。同一存储器块中的晶体管单元的源极通过控制栅极连接到主源极线，漏极也如此。列方向上的独立源和漏极被设计用于基于位的写入能力。所选择的晶体管单元的写入，例如擦除或编程使用Fowler-Nordheim隧道方法，并且可以由于施加到未选择的晶体管单元的编程或擦除禁止电压而实现。还公开了用于基于位的写入的相关电路，以及编程和擦除存储器单元阵列的方法，具有过程编程和过擦除修复能力。

89. 发明授权

US5646890A Flexible byte-erase flash memory and decoder 失效
标题翻译：灵活的字节擦除闪存和解码器
公开(公告)号：US5646890A
公开(公告)日：1997-07-08
申请号：US624322
申请日：1996-03-29
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/10 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/34 , G11C16/00
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C8/10 , G11C2211/5642 , G11C2216/20 , G11C8/00
摘要： A flexible word-erase flash memory includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline. A second bank of flash transistors form a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline. A bitline decoder is coupled to the bitlines and configured to receive a bitline address signal and to decode the bitline address signal to select a predetermined plurality of bitlines. A sourceline latch is coupled to the first sourceline and the second sourceline and configured to latch a selected sourceline to selectively provide a sourceline erase voltage on the selected sourceline. Advantages of the invention include reduced stress on transistors not selected to be erased. This reduces program time by selectively erasing only those transistors needing reprogramming and promotes longevity of the flash memory transistors by erasing only the selected transistors.
摘要翻译：灵活的字擦除闪速存储器包括形成多行和多列的第一组闪存晶体管，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到公共位线和第一组中的晶体管的源极都耦合到第一源极线。闪存晶体管的第二组形成多个行和多个列，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到公共位线和晶体管的源极第二个银行都连接到第二个来源线。字线解码器耦合到字线并且被配置为接收字线地址信号并解码字线地址信号以选择字线。位线解码器耦合到位线并且被配置为接收位线地址信号并且解码位线地址信号以选择预定的多个位线。源极线锁存器耦合到第一源极线路和第二源极线路，并被配置为锁存所选择的源极线以选择性地在所选择的源极线路上提供源极线路擦除电压。本发明的优点包括未选择被擦除的晶体管上的应力降低。这通过仅选择性地擦除需要重新编程的晶体管并通过仅擦除所选择的晶体管来促进闪存晶体管的寿命来减少编程时间。

90. 发明授权

US4731570A Electrical drive circuit for a variable-speed switched reluctance motor 失效
标题翻译：用于变速开关磁阻电机的电驱动电路
公开(公告)号：US4731570A
公开(公告)日：1988-03-15
申请号：US943213
申请日：1986-09-08
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： H02P25/08 , H02P8/00
CPC分类号： H02P25/0925
摘要： An electrical drive circuit for a variable-speed switched reluctance motor having a bifilar winding is provided. First, second, and third thyristor switches (5,7,10) each having respective firing circuits (6,8,11) are associated with the motor. A commutation capacitor device (9) is associated with one of the thyristor switches (5,7,10). A sensing means (33) determines the direction of current flow through the commutation capacitor device (9), and a control system (20) prevents the first and third thyristor switches (5,10) from conducting when the second thyristor switch (7) is conducting and prevents the first and second thyristor switches (5,7) from conducting when the third thyristor switch (10) is conducting.
摘要翻译： PCT No.PCT / US86 / 01846 Sec。 371日期1986年9月8日第 102（e）1986年9月8日PCT PCT。1986年9月8日PCT公布。出版物WO87 / 01530 日期为1987年3月12日。提供具有双线绕组的变速开关磁阻电动机的电驱动电路。每个具有各自的点火电路（6,8,11）的第一，第二和第三晶闸管开关（5,7,10）与电动机相关联。换向电容器装置（9）与晶闸管开关（5,7,10）中的一个相关联。感测装置（33）确定通过换向电容器装置（9）的电流的方向，并且当第二晶闸管开关（7）被控制时，控制系统（20）防止第一和第三晶闸管开关（5,10）导通，正在导通并且防止当第三晶闸管开关（10）导通时第一和第二晶闸管开关（5,7）导通。

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