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81. 发明申请

US20070153617A1 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US20070153617A1
公开(公告)日：2007-07-05
申请号：US11652012
申请日：2007-01-11
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C7/02
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.
摘要翻译：采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。由于从读数导出的阵列噪声减小，因此边缘被增强。另外，DRAM的存取时间也减少了。

82. 发明授权

US07239562B2 Semiconductor device 有权
公开(公告)号：US07239562B2
公开(公告)日：2007-07-03
申请号：US11313833
申请日：2005-12-22
申请人： Riichiro Takemura
发明人： Riichiro Takemura
IPC分类号： G11C7/10
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2013/0057
摘要： In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.

83. 发明申请

US20060227648A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060227648A1
公开(公告)日：2006-10-12
申请号：US11399397
申请日：2006-04-07
申请人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
发明人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
IPC分类号： G11C8/00
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108
摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
摘要翻译：在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

84. 发明授权

US06917552B2 Semiconductor device using high-speed sense amplifier 失效
公开(公告)号：US06917552B2
公开(公告)日：2005-07-12
申请号：US10671464
申请日：2003-09-29
申请人： Riichiro Takemura , Tomonori Sekiguchi , Takeshi Sakata
发明人： Riichiro Takemura , Tomonori Sekiguchi , Takeshi Sakata
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C11/4097
摘要： Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.

85. 发明申请

US20050146960A1 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US20050146960A1
公开(公告)日：2005-07-07
申请号：US11048915
申请日：2005-02-03
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/409 , G11C11/4096 , G11C15/00
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.
摘要翻译：采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。由于从读数导出的阵列噪声减小，因此边缘被增强。另外，DRAM的存取时间也减少了。

86. 发明申请

US20050056876A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050056876A1
公开(公告)日：2005-03-17
申请号：US10975494
申请日：2004-10-29
申请人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
发明人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
IPC分类号： G11C11/401 , G11C7/18 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/119
CPC分类号： H01L27/108 , G11C7/18 , G11C11/403 , G11C11/406 , G11C11/40615 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10897 , Y10S257/905 , Y10S257/906
摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
摘要翻译：提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期，实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低，高速读出时间，确保自刷新时间长的刷新周期。采用单交点单元两个单元/位方法的DRAM具有采用单交叉6 F 2单元的双单元结构，其结构是：存储单元布置在对应于a 位线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。另外，硅衬底中的有源区域形成每个存储单元的晶体管的源极，沟道和漏极，相对于位线对的方向倾斜地形成。

87. 发明授权

US06538912B2 Semiconductor device 有权
公开(公告)号：US06538912B2
公开(公告)日：2003-03-25
申请号：US10139330
申请日：2002-05-07
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

88. 发明授权

US06400596B2 Semiconductor memory device using open data line arrangement 有权
标题翻译：半导体存储器件采用开放数据线布置
公开(公告)号：US06400596B2
公开(公告)日：2002-06-04
申请号：US09725107
申请日：2000-11-29
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
摘要翻译：当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线内存阵列因此，提供了根据本发明的半导体器件。在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统放置即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。

89. 发明授权

US09725753B2 Biomolecule information analysis device 有权
公开(公告)号：US09725753B2
公开(公告)日：2017-08-08
申请号：US14122206
申请日：2011-05-31
申请人： Kazuo Ono , Tatsuo Nakagawa , Yoshimitsu Yanagawa , Takayuki Kawahara , Akira Kotabe , Riichiro Takemura
发明人： Kazuo Ono , Tatsuo Nakagawa , Yoshimitsu Yanagawa , Takayuki Kawahara , Akira Kotabe , Riichiro Takemura
IPC分类号： C12Q1/68 , G01N33/487
CPC分类号： C12Q1/68 , C12Q1/6869 , G01N33/48721 , C12Q2565/631
摘要： Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. 1).

90. 发明授权

US09257483B2 Magnetic memory, method of manufacturing the same, and method of driving the same 有权
标题翻译：磁记忆体，其制造方法及其驱动方法
公开(公告)号：US09257483B2
公开(公告)日：2016-02-09
申请号：US13522076
申请日：2011-01-13
申请人： Takashi Ishigaki , Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Kenchi Ito
发明人： Takashi Ishigaki , Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Kenchi Ito
IPC分类号： G11C11/00 , H01L27/22 , G11C11/16 , H01L43/08 , H01L43/12 , H01L29/82 , G11C11/56
CPC分类号： H01L27/228 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/5607 , H01L29/82 , H01L43/08 , H01L43/12
摘要： There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other.
摘要翻译：提供了一种使用自旋注入磁化反转型的磁阻效应元件的磁存储器，其中多值操作是可能的，其制造和操作简单。优选的目的是通过提供两个或更多个彼此串联电连接的磁阻效应元件来解决，并且根据串联连接的元件中承载的电流的方向选择串联元件之一，其大小及其电流的顺序用于执行写入操作。例如，通过将具有相同膜结构的各个磁阻效应元件的平面面积尺寸相互分离来解决，以便区分由相应的磁化反转引起的电阻变化量和相应磁化反转所需的阈值电流值。

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