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81. 发明申请

US20110108905A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110108905A1
公开(公告)日：2011-05-12
申请号：US13007258
申请日：2011-01-14
申请人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

82. 发明授权

US07855918B2 Method for programming a memory structure 有权
标题翻译：用于编程存储器结构的方法
公开(公告)号：US07855918B2
公开(公告)日：2010-12-21
申请号：US12144645
申请日：2008-06-24
申请人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
发明人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译：存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元。

83. 发明授权

US07791948B2 Channel carrier discharging in a NAND flash memory on an insulating substrate or layer 失效
标题翻译：通道载体在绝缘基板或层上的NAND闪速存储器中放电
公开(公告)号：US07791948B2
公开(公告)日：2010-09-07
申请号：US12165211
申请日：2008-06-30
申请人： Riichiro Shirota , Fumitaka Arai
发明人： Riichiro Shirota , Fumitaka Arai
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/10
摘要： A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.
摘要翻译：半导体存储器件包括：设置在绝缘基板或绝缘层上的半导体层; 在半导体层中限定的有源区域，其中埋设有器件绝缘膜; 以及形成在有源区上的NAND单元单元，每个NAND单元单元包括串联连接的多个电可重写和非易失性存储单元，每个NAND单元单元的两端耦合到源极线和位线，其中，器件具有这样的载流子放电模式，以将NAND单元单元中的沟道载流子放电到源极线和位线中的至少一个。

84. 发明授权

US07755134B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07755134B2
公开(公告)日：2010-07-13
申请号：US11765881
申请日：2007-06-20
申请人： Masaru Kito , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
发明人： Masaru Kito , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
IPC分类号： H01L27/115
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42336
摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.
摘要翻译：非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

85. 发明授权

US07521749B2 Nonvolatile semiconductor memory device including improved gate electrode 失效
标题翻译：包括改进的栅电极的非易失性半导体存储器件
公开(公告)号：US07521749B2
公开(公告)日：2009-04-21
申请号：US11877075
申请日：2007-10-23
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.
摘要翻译：通过栅极绝缘膜在半导体衬底上形成浮栅。扩散层在半导体衬底中的浮置栅极的相对侧上形成为源区或漏极区。第一和第二控制栅极通过栅极间绝缘膜与浮动栅极的相对侧上的两个扩散层相对形成，以驱动浮置栅极。

86. 发明授权

US07459748B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07459748B2
公开(公告)日：2008-12-02
申请号：US11549770
申请日：2006-10-16
申请人： Riichiro Shirota , Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Makoto Mizukami , Kiyotaka Miyano , Ichiro Mizushima
发明人： Riichiro Shirota , Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Makoto Mizukami , Kiyotaka Miyano , Ichiro Mizushima
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.
摘要翻译：半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

87. 发明申请

US20080012061A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080012061A1
公开(公告)日：2008-01-17
申请号：US11687758
申请日：2007-03-19
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮置栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

88. 发明申请

US20070291539A1 Nonvolatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070291539A1
公开(公告)日：2007-12-20
申请号：US11699334
申请日：2007-01-30
申请人： Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
发明人： Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
IPC分类号： G11C11/34 , H01L21/822
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.
摘要翻译：非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域位置高她比第三个导电区域。

89. 发明授权

US07310270B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07310270B2
公开(公告)日：2007-12-18
申请号：US11737154
申请日：2007-04-19
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选择的存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

90. 发明授权

US07139201B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US07139201B2
公开(公告)日：2006-11-21
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

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