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81. 发明授权

US5864160A Transistor device with reduced hot carrier injection effects 失效
标题翻译：具有减少热载流子注入效应的晶体管器件
公开(公告)号：US5864160A
公开(公告)日：1999-01-26
申请号：US653147
申请日：1996-05-24
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/76 , H01L23/62
CPC分类号： H01L29/512 , H01L21/28167 , H01L29/4991 , H01L29/515 , H01L29/66575
摘要： A MOS transistor includes a void space as part of the gate oxide layer on the drain end of the transistor. The void space replaces a region of the gate oxide layer so that no oxide is present for injection of hot carriers. The presence of the void space, preferably containing a vacuum, also reduces the total gate capacitance of the device. The void space is formed by chemical etching of the gate oxide layer and void space sealing during device manufacture.
摘要翻译： MOS晶体管包括作为晶体管的漏极端上的栅极氧化物层的一部分的空隙空间。空隙空间取代了栅极氧化物层的区域，使得不存在用于注入热载流子的氧化物。优选含有真空的空隙空间的存在也降低了器件的总栅极电容。在器件制造期间通过化学蚀刻栅极氧化物层和空隙空间密封形成空隙空间。

82. 发明授权

US4761386A Method of fabricating conductive non-metallic self-passivating non-corrodable IC bonding pads 失效
标题翻译：导电非金属自钝化非可腐蚀IC焊盘的制造方法
公开(公告)号：US4761386A
公开(公告)日：1988-08-02
申请号：US888553
申请日：1986-07-21
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L23/485 , H01L23/532 , H01L21/66
CPC分类号： H01L24/05 , H01L23/53271 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/85805 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , Y10S148/125 , Y10S228/904
摘要： A monolithic silicon integrated circuit chip is provided with a conductive passivating coating over the metal bonding pads. The coating is composed of doped polysilicon or metal silicide. Such materials provide a self-passivating, non-corrodable surface capable of forming a conventional eutectic bond to a connecting wire. A moat is etched through this layer outside the confines of the bonding pad so that they can be electrically isolated. Eutectic wire bonds are then made to the coating where they would ordinarily be made to the pad metal. Since the passivating coating fully covers the bonding pad a substantial increase in passivation occurs. If desired the passivating coating can be overcoated with a thin metal layer to facilitate probing of the circuits in wafer form.
摘要翻译：单片硅集成电路芯片在金属接合焊盘上设置有导电钝化涂层。涂层由掺杂多晶硅或金属硅化物组成。这样的材料提供能够形成常规共晶键到连接线的自钝化的非腐蚀性表面。在接合焊盘的限制之外，通过该层蚀刻护环，使得它们可以被电隔离。然后将共晶线接合件制成涂层，通常将其焊接到焊盘金属上。由于钝化涂层完全覆盖焊盘，所以发生钝化的显着增加。如果需要，可以用薄金属层覆盖钝化涂层，以便于以晶片形式探测电路。

83. 发明授权

US08368219B2 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08368219B2
公开(公告)日：2013-02-05
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

84. 发明授权

US08049334B1 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08049334B1
公开(公告)日：2011-11-01
申请号：US12843131
申请日：2010-07-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

85. 发明授权

US06979642B1 Method of self-annealing conductive lines that separates grain size effects from alloy mobility 有权
标题翻译：将晶粒尺寸效应与合金迁移率分离的导电线自退火方法
公开(公告)号：US06979642B1
公开(公告)日：2005-12-27
申请号：US10628733
申请日：2003-07-28
申请人： Matthew S. Buynoski , Connie Pin-Chin Wang , Paul R. Besser , Minh Q. Tran
发明人： Matthew S. Buynoski , Connie Pin-Chin Wang , Paul R. Besser , Minh Q. Tran
IPC分类号： H01L21/283 , H01L21/288 , H01L21/321 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/321 , H01L21/76877
摘要： A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.
摘要翻译：形成诸如铜导电结构，管线或通孔的导电结构的方法被优化用于合金元件的大晶粒生长和分布。合金元素可以减少与导电结构相关的电迁移问题。导电结构在较长时间内在低温过程中自退火或首先退火。利用另一退火来分配合金元素。

86. 发明授权

US06861349B1 Method of forming an adhesion layer with an element reactive with a barrier layer 失效
标题翻译：用与阻挡层反应的元件形成粘合层的方法
公开(公告)号：US06861349B1
公开(公告)日：2005-03-01
申请号：US10145944
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76859 , H01L21/76873 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元素进入阻挡材料层上的界面层，在界面层上沉积合金层。植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

87. 发明授权

US06852586B1 Self assembly of conducting polymer for formation of polymer memory cell 有权
标题翻译：用于形成聚合物记忆体的导电聚合物的自组装
公开(公告)号：US06852586B1
公开(公告)日：2005-02-08
申请号：US10677042
申请日：2003-10-01
申请人： Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Nicholas H. Tripsas
发明人： Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Nicholas H. Tripsas
IPC分类号： G11C13/02 , H01L27/28 , H01L51/40 , H01L21/8234
CPC分类号： G11C13/0069 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2013/009 , G11C2213/56 , G11C2213/71 , H01L27/28 , H01L51/0012
摘要： The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that a shortest conductive path can be achieved. The method includes depositing a concentrated solution of conducting polymer on a conductive surface, applying heat and optionally a vacuum, and permitting the conducting polymer to self-assemble into an organic semiconductor. The organic semiconductor can be employed within single and multi-cell memory devices by forming a structure with two or more electrodes while employing the organic semiconductor along with a passive device between the electrodes. A partitioning component can be integrated with the memory device to facilitate programming and stacking of additional memory cells on top of or in association with previously formed cells.
摘要翻译：本发明提供可用作存储单元的选择性导电的有机半导体（例如，聚合物）器件。包括导电聚合物的聚合物溶液相对于导电电极自组装。该过程提供自组装，使得可以实现最短的导电路径。该方法包括将导电聚合物的浓缩溶液沉积在导电表面上，施加热量和任选的真空，并允许导电聚合物自组装成有机半导体。有机半导体可以在单电池和多电池存储器件中使用，通过形成具有两个或多个电极的结构，同时在电极之间使用有机半导体以及无源器件。分区组件可以与存储器件集成，以便于在先前形成的单元之上或与之前相关联的附加存储器单元的编程和堆叠。

88. 发明授权

US06835655B1 Method of implanting copper barrier material to improve electrical performance 失效
标题翻译：注入铜阻挡材料以改善电气性能的方法
公开(公告)号：US06835655B1
公开(公告)日：2004-12-28
申请号：US09994397
申请日：2001-11-26
申请人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin
发明人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin
IPC分类号： H01L2144
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76859 , H01L2924/0002 , H01L2924/00
摘要： A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper layer to form a barrier material layer separating the via from the copper layer, implanting a metal species into the barrier material layer, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted metal species can make the barrier material layer more resistant to copper diffusion from the copper layer.
摘要翻译：在集成电路制造工艺中注入铜阻挡材料以提高电性能的方法可以包括在集成电路基板上提供铜层，在位于铜层上方的通孔的底部和侧面提供阻挡材料以形成屏障将所述通孔与所述铜层分离的材料层，将金属物质注入到所述阻挡材料层中，以及在所述通孔上方提供导电层，使得所述通孔将所述导电层电连接到所述铜层。注入的金属物质可以使阻挡材料层更能抵抗铜层从铜层扩散。

89. 发明授权

US06787436B1 Silicide-silicon contacts for reduction of MOSFET source-drain resistances 失效
标题翻译：用于降低MOSFET源极 - 漏极电阻的硅化硅 - 硅触点
公开(公告)号：US06787436B1
公开(公告)日：2004-09-07
申请号：US10147382
申请日：2002-05-15
申请人： Matthew S. Buynoski , Witold Maszara
发明人： Matthew S. Buynoski , Witold Maszara
IPC分类号： H04L21425
CPC分类号： H01L21/28518
摘要： Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.
摘要翻译：提出了降低由硅化物和掺杂硅区域之间的界面呈现的接触电阻的方法。在第一种方法中，硅化物层和掺杂的硅区形成界面。将仅有损坏的物质或重的金属通过硅化物层注入到与界面紧邻的掺杂硅区域中。在第二种方法中，在形成硅化物之前，将第二种金属加入难熔金属中。在难熔金属和掺杂硅区域退火之后，第二金属扩散到紧邻界面的掺杂硅化物区域，而不在硅化物中形成附加相。

90. 发明授权

US06765303B1 FinFET-based SRAM cell 有权
标题翻译：基于FinFET的SRAM单元
公开(公告)号：US06765303B1
公开(公告)日：2004-07-20
申请号：US10429697
申请日：2003-05-06
申请人： Zoran Krivokapic , Judy Xilin An , Matthew S. Buynoski
发明人： Zoran Krivokapic , Judy Xilin An , Matthew S. Buynoski
IPC分类号： H01L2711
CPC分类号： B82Y10/00 , G11C11/412 , H01L27/11 , H01L29/66818 , H01L29/785 , Y10S257/903
摘要： A SRAM cell includes a single FinFET and two resonant tunnel diodes. The FinFet has multiple channel regions formed from separate fins. The resonant tunnel diodes may be formed from FinFET type fins. In particular, the resonant diodes may includes a thin, undoped silicon region surrounded by a dielectric. The SRAM cell is small and provides fast read/write access times.
摘要翻译： SRAM单元包括单个FinFET和两个谐振隧道二极管。 FinFet具有由独立翅片形成的多个通道区域。谐振隧道二极管可以由FinFET型鳍形成。特别地，谐振二极管可以包括由电介质围绕的薄的未掺杂的硅区域。 SRAM单元很小，并提供快速的读/写访问时间。

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