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81. 发明申请

US20110075489A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110075489A1
公开(公告)日：2011-03-31
申请号：US12718428
申请日：2010-03-05
申请人： Takashi YAMANE , Atsuhiro Sato
发明人： Takashi YAMANE , Atsuhiro Sato
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/3427
摘要： Two or more writing prohibition voltages are applied to bit lines connected to memory cell transistors corresponding to the writing voltage of word lines in a writing operation to write data in the memory cell transistors, while increasing the writing voltage of the word line in a stepwise. Two or more selection gate line voltages, corresponding to the writing prohibition voltages applied to the bit lines, are applied to the gates of selection gate transistors.
摘要翻译：在写入操作中将写入数据写入存储单元晶体管中的两个或多个写入禁止电压施加到与字线的写入电压对应的存储单元晶体管连接的位线，同时逐步增加字线的写入电压。与施加到位线的写入禁止电压对应的两个或多个选择栅极线电压被施加到选择栅极晶体管的栅极。

82. 发明授权

US07560320B2 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07560320B2
公开(公告)日：2009-07-14
申请号：US11947396
申请日：2007-11-29
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

83. 发明授权

US07183615B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US07183615B2
公开(公告)日：2007-02-27
申请号：US10868773
申请日：2004-06-17
申请人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
发明人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L27/115 , H01L29/42324 , Y10T428/24256
摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
摘要翻译：半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层，在电极间电介质上。这里，器件隔离膜的上角被倒角。

84. 发明申请

US20050045966A1 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US20050045966A1
公开(公告)日：2005-03-03
申请号：US10868773
申请日：2004-06-17
申请人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
发明人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
IPC分类号： H01L21/76 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/82 , H01L29/76
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L27/115 , H01L29/42324 , Y10T428/24256
摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
摘要翻译：半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层，在电极间电介质上。这里，器件隔离膜的上角被倒角。

85. 发明授权

US07928496B2 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07928496B2
公开(公告)日：2011-04-19
申请号：US11808147
申请日：2007-06-07
申请人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
发明人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.
摘要翻译：公开了一种具有高电荷保持特性并且能够改善设置在电荷存储层和控制栅电极之间的电介质膜的漏电特性的非易失性半导体存储器件及其制造方法。根据一个方面，提供了一种半导体存储器件，包括设置在半导体衬底上的第一绝缘体上的第一电极，设置在第一电极上的第二绝缘体，设置在第二绝缘体上的第二电极和设置在第二绝缘体上的扩散层半导体衬底，其中包括比在化学计量的氮化硅膜中含有更多的硅的富含硅的氮化硅膜的第二绝缘体和形成在富硅氮化硅膜上的氧化硅膜，并且其中富硅氮化硅膜的硅浓度和氮浓度的比率设定为1:0.9至1:1.2。

86. 发明申请

US20070287253A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070287253A1
公开(公告)日：2007-12-13
申请号：US11808147
申请日：2007-06-07
申请人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
发明人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.
摘要翻译：公开了一种具有高电荷保持特性并且能够改善设置在电荷存储层和控制栅电极之间的电介质膜的漏电特性的非易失性半导体存储器件及其制造方法。根据一个方面，提供了一种半导体存储器件，包括设置在半导体衬底上的第一绝缘体上的第一电极，设置在第一电极上的第二绝缘体，设置在第二绝缘体上的第二电极和设置在第二绝缘体上的扩散层半导体衬底，其中包括比在化学计量的氮化硅膜中含有更多的硅的富含硅的氮化硅膜的第二绝缘体和形成在富硅氮化硅膜上的氧化硅膜，并且其中富硅氮化硅膜的硅浓度和氮浓度的比率设定为1:0.9至1:1.2。

87. 发明授权

US07031195B2 Nonvolatile semiconductor memory having a control gate driver transistor whose gate insulator thickness is greater than that of a select gate driver transistor 失效
标题翻译：具有栅极绝缘体厚度大于选择栅极驱动晶体管栅极绝缘体厚度的控制栅极驱动晶体管的非易失性半导体存储器
公开(公告)号：US07031195B2
公开(公告)日：2006-04-18
申请号：US10948295
申请日：2004-09-24
申请人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
发明人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
IPC分类号： G11C16/08
CPC分类号： G11C16/06 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11546
摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.
摘要翻译：非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。

88. 发明授权

US06927139B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
公开(公告)号：US06927139B2
公开(公告)日：2005-08-09
申请号：US10717719
申请日：2003-11-21
申请人： Masayuki Tanaka , Atsuhiro Sato , Hiroki Yamashita , Ichiro Mizushima , Yoshio Ozawa
发明人： Masayuki Tanaka , Atsuhiro Sato , Hiroki Yamashita , Ichiro Mizushima , Yoshio Ozawa
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.

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