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    • 82. 发明授权
    • Arithmetic unit capable of performing concurrent operations for high
speed operation
    • 算术单元能够执行高速运行的并发操作
    • US5408426A
    • 1995-04-18
    • US037654
    • 1993-03-17
    • Hidehito TakewaHiromichi YamadaTakashi HottaKotaro Shimamura
    • Hidehito TakewaHiromichi YamadaTakashi HottaKotaro Shimamura
    • G06F7/50G06F7/52G06F7/535G06F7/537G06F7/57G06F7/38
    • G06F7/535G06F7/483G06F7/485G06F7/5375G06F7/4873G06F7/49936G06F7/49957
    • An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand. The rounding device executes at least part of the rounding process by the use of the numerical values not yet subjected to the normalizing process, in parallel with the execution of the adder-subtracter or the normalizer.
    • 接受两个数值并通过使用两个数值执行操作的算术单元具有加法器 - 减法器,用于基于从接受的两个数值直接或间接获得的两个数值来执行加法或减法运算; 用于执行归一化处理的归一化器,其中相加或相减结果的尾数部分被移位,使得在结果中重新显现的高阶数字可以到达预定位置,并且其中结果的指数部分 根据尾数部分的偏移位置的数量进行校正; 以及用于执行舍入处理的舍入装置,其中,在相加或相减结果的尾数部分超过预定数量的数字的条件下,尾数部分的位数根据预先指定的舍入模式而减少。 舍入装置与加法器 - 减法器或归一化器的执行并行,通过使用尚未进行归一化处理的数值来执行舍入处理的至少一部分。
    • 88. 发明授权
    • Computer system including an interrupt controller
    • 计算机系统包括一个中断控制器
    • US08589612B2
    • 2013-11-19
    • US13106788
    • 2011-05-12
    • Hiromichi YamadaKotaro ShimamuraNobuyasu KanekawaYuichi Ishiguro
    • Hiromichi YamadaKotaro ShimamuraNobuyasu KanekawaYuichi Ishiguro
    • G06F13/24
    • G06F13/24G06F11/1641G06F2201/845
    • A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.
    • 提供一种缩短CPU的待机时间并提高从性能模式(并行操作)切换到安全模式(主/检测器操作)时的CPU处理效率的计算机系统。 在一个计算机系统中,包括:至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器,用于相互比较CPU的输出,分别由CPU执行相互不同的处理的性能模式之间进行切换,以提高CPU的性能和执行相同处理的安全模式,并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。
    • 89. 发明授权
    • Multi-core microcontroller having comparator for checking processing result
    • 具有用于检查处理结果的比较器的多核微控制器
    • US08433955B2
    • 2013-04-30
    • US12610422
    • 2009-11-02
    • Hiromichi YamadaKotaro ShimamuraKesami HagiwaraYoshikazu KiyoshigeYuichi Ishiguro
    • Hiromichi YamadaKotaro ShimamuraKesami HagiwaraYoshikazu KiyoshigeYuichi Ishiguro
    • G06F11/00
    • G06F11/1608G06F11/004G06F11/1641G06F11/1687G06F2201/83G06F2201/845
    • A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.
    • 一种微控制器,其能够通过由多个CPU执行不同的程序来提高处理性能,并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统,每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较,当比较结果表示不匹配时,可以检测出异常处理。 即使当多个CPU异步执行相同的处理时,获得相同处理结果的定时也是不同的,因此压缩机进行压缩,因此可以容易地将它们的处理结果进行比较。 此外,由于在从所有CPU给出比较使能时能够进行比较器的比较,所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。