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81. 发明申请

US20060285375A1 Semiconductor memory and method for manufacturing the semiconductor memory 审中-公开
标题翻译：半导体存储器及半导体存储器的制造方法
公开(公告)号：US20060285375A1
公开(公告)日：2006-12-21
申请号：US11342533
申请日：2006-01-31
申请人： Masato Endo , Atsuhiro Sato , Fumitaka Arai , Tooru Maruyama
发明人： Masato Endo , Atsuhiro Sato , Fumitaka Arai , Tooru Maruyama
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A semiconductor memory includes a semiconductor region, floating gate electrodes arranged in a matrix on the semiconductor region through a tunnel insulating layer, inter-gate insulating layers disposed only on the plurality of floating gate electrodes, respectively, control gate electrodes disposed on the plurality of inter-gate insulating layers, respectively, and isolation insulators extending between arrangements of the control gate electrodes along a column direction of the matrix, each of the isolation insulators penetrating into the semiconductor region so as to electrically isolate the inter-gate insulating layers from each other in the column direction.
摘要翻译：半导体存储器包括半导体区域，通过隧道绝缘层在半导体区域上以矩阵布置的浮置栅电极，分别仅设置在多个浮置栅电极上的栅极间绝缘层，分别设置在多个栅绝缘层和隔离绝缘体，隔离绝缘体沿着矩阵的列方向在控制栅电极的布置之间延伸，每个隔离绝缘体穿透到半导体区域中，以便将栅间绝缘层与每个绝缘层电隔离其他在列方向。

82. 发明授权

US07092294B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07092294B2
公开(公告)日：2006-08-15
申请号：US11330086
申请日：2006-01-12
申请人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
发明人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.
摘要翻译：半导体存储器包括具有存储单元单元的存储单元阵列，存储单元单元由连接在列中的存储单元晶体管构成，其具有设置在浮置栅极两侧的第一和第二控制栅极，水平布置，第一端连接到经由第一选择栅晶体管的位线，以及经由第二选择栅极晶体管连接到源极线的第二端。布置在同一行中的存储单元晶体管的第一和第二控制栅极分别连接到一行中的第一和第二控制栅极线。它还包括升压电路，其从电源产生写入电压，多电平中间电压和位线电压，以及提供有写入电压和多电平中间电压的行解码器，以选择第一和第二控制门。

83. 发明申请

US20060120155A1 Nonvolatile semiconductor memory 失效
公开(公告)号：US20060120155A1
公开(公告)日：2006-06-08
申请号：US11330086
申请日：2006-01-12
申请人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
发明人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.

84. 发明授权

US07031195B2 Nonvolatile semiconductor memory having a control gate driver transistor whose gate insulator thickness is greater than that of a select gate driver transistor 失效
标题翻译：具有栅极绝缘体厚度大于选择栅极驱动晶体管栅极绝缘体厚度的控制栅极驱动晶体管的非易失性半导体存储器
公开(公告)号：US07031195B2
公开(公告)日：2006-04-18
申请号：US10948295
申请日：2004-09-24
申请人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
发明人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
IPC分类号： G11C16/08
CPC分类号： G11C16/06 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11546
摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.
摘要翻译：非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。

85. 发明授权

US07020025B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US07020025B2
公开(公告)日：2006-03-28
申请号：US10944940
申请日：2004-09-21
申请人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
发明人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.

86. 发明授权

US06927139B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
公开(公告)号：US06927139B2
公开(公告)日：2005-08-09
申请号：US10717719
申请日：2003-11-21
申请人： Masayuki Tanaka , Atsuhiro Sato , Hiroki Yamashita , Ichiro Mizushima , Yoshio Ozawa
发明人： Masayuki Tanaka , Atsuhiro Sato , Hiroki Yamashita , Ichiro Mizushima , Yoshio Ozawa
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.

87. 发明授权

US06921960B2 Capacitor element with an opening portion formed in a peripheral circuit 有权
标题翻译：具有形成在外围电路中的开口部分的电容器元件
公开(公告)号：US06921960B2
公开(公告)日：2005-07-26
申请号：US09984718
申请日：2001-10-31
申请人： Masayuki Ichige , Riichiro Shirota , Kikuko Sugimae , Atsuhiro Sato , Yuji Takeuchi
发明人： Masayuki Ichige , Riichiro Shirota , Kikuko Sugimae , Atsuhiro Sato , Yuji Takeuchi
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/08 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/00
CPC分类号： H01L27/11526 , H01L27/0805 , H01L27/105 , H01L27/11531
摘要： A semiconductor device includes a structure in which a first electrode layer, an inter-electrode insulating film and a second electrode layer are laminated in a main circuit in this order, and includes a capacitor element having a lower electrode formed of the same layer as the first electrode layer, a charge storage layer formed of the same layer as the inter-electrode insulating film, and an upper electrode formed of the second electrode layer. The semiconductor device further includes an opening portion formed in the charge storage layer, the opening portion having a bottom to which the lower electrode is exposed, and a first region electrically connected to the lower electrode via the opening portion and electrically isolated from the upper electrode, the first region being formed of the same layer as the second electrode layer.
摘要翻译：半导体器件包括其中第一电极层，电极间绝缘膜和第二电极层依次层叠在主电路中的结构，并且包括电容器元件，其具有由与第一电极层相同的层形成的下电极第一电极层，由与电极间绝缘膜相同的层形成的电荷存储层和由第二电极层形成的上电极。半导体装置还包括形成在电荷存储层中的开口部分，开口部分具有露出下部电极的底部，以及经由开口部分电连接到下部电极并与上部电极电隔离的第一区域所述第一区域由与所述第二电极层相同的层形成。

88. 发明授权

US06853029B2 Non-volatile semiconductor memory device with multi-layer gate structure 失效
标题翻译：具有多层栅极结构的非易失性半导体存储器件
公开(公告)号：US06853029B2
公开(公告)日：2005-02-08
申请号：US10155086
申请日：2002-05-28
申请人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
发明人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.
摘要翻译：半导体器件包括半导体衬底，源极和漏极区，沟道区，栅极绝缘膜，电荷存储层和控制栅电极。源区和漏区包括第一导电类型的第一杂质。沟道区域包括第二导电类型的第二杂质。栅极绝缘膜包括位于沟道区域的至少一部分正上方的区域中的第二杂质。电荷存储层形成在栅极绝缘膜上。控制栅电极设置在电荷存储层上。控制栅电极形成在电荷存储层上，并且通过设置在电荷存储层的一部分上的连接部分电连接到电荷存储层，所述连接部位于栅极绝缘区域的至少一部分的正上方膜包括第二杂质。

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